riscv-non-isa/riscv-trace-spec

Entering Debug Mode

zhonghochen opened this issue · 1 comments

zhonghochen commented

https://github.com/riscv/riscv-trace-spec/blob/9896e28a5b35d86178c08e77e0ae6daaafeba072/ingressPort.tex#L1

What should the hart to encoder interface output when a hart enters debug mode?
There are 6 causes that a hart enters debug mode: ebreak, trigger, haltreq, step, resethaltreq, halt group.

gajinderpanesar commented

There is a 'halted' sideband signal which should help in this