riscv-non-isa/riscv-trace-spec

Request for new field in format 3, subformat 1 (exception) message. Section 7.3

bmcspadd-seagate opened this issue · 0 comments

During debug of exception tracing, we want to easily trace through exceptions.
The proposed spec adds support for tracing through an "illegal instruction" exception
by providing the address of the illegal instruction in the tvalepc field. This allows
us to easily find the offending address when going through an uninferrable jump
to the offending address.

We think this same behaviour should be extended to all exceptions. And we also
believe that the contents of the tval register should also be visible.

As such, we are requesting that the format 3, subformat 1 message contain both
the tval and epc contents in the trace message.

Advantages:

  • Debug of exception tracing is much cleaner and easier. There is no need to
    instrument code in order to obtain the epc during trace (which would require
    data trace to be turned on).

Disadvantages:

  • This adds extra bits to the payload, which will negatively affect trace bandwidth
    utilization. However, we believe that exceptions are an exceptional case and as such,
    will not be frequently encountered.