Issues
- 0
SPIKE + PK C++ `iostream` support
#1778 opened by mp-17 - 0
Installation Guide for v1.1.0
#1775 opened by zaki-29871 - 1
Bug Fix Suggestion for v1.1.0
#1774 opened by zaki-29871 - 3
`fmv.w.x` is illegal?
#1773 opened by Donkey-Hao - 3
- 1
`fdiv.s` with a dynamic rounding mode set to `REN` on the spike results in a incorrect rounding
#1772 opened by riscv914 - 4
- 1
- 2
Zicntr not listed as supported extension
#1761 opened by christian-herber-nxp - 8
- 1
- 3
Segmentation Fault when interrupt handled while interrupts are disabled in machine mode
#1752 opened by mkorbel1 - 2
SPIKE functions use in System verilog
#1743 opened by svasekar - 2
From double trap spec, we saw that Ssdbltrp adds an SDT field to sstatus. But will mstatus has this bit?
#1751 opened by Madman-Hugo - 5
Need assistance for Executing my targeted workload on spike RISC-V ISA after adding custom trigonometric Instructions
#1747 opened by baul-iisc - 5
Why menvcfg.pbmt is set 1 on reset ?
#1745 opened by chihminchao - 0
- 0
spike.cfg : remote_bitbang host localhost should be remote_bitbang_host in OPENOCD's
#1739 opened by yesuweiYYYY - 0
Possible to forward a Ctrl-C to the running program?
#1738 opened by wsong83 - 0
htif : elf load , invalid address
#1737 opened by svasekar - 1
Dose write-only operation to csr_seed trigger illegal instruction exception ?
#1728 opened by chihminchao - 2
Deprecated dcsr.halt
#1727 opened by YenHaoChen - 1
Spike behaviour: vector register overlap
#1699 opened by UzairHumayun - 0
Incorrect IRQ priority with LCOF
#1725 opened by JJ-Gaisler - 0
Dependency file in makefile is missing
#1723 opened by hegdeabhi - 0
spike cache model
#1720 opened by ztjjj9 - 3
vsetivli yields illegal instruction exception
#1698 opened by Maor545 - 9
sbbusyerror model breaks openOCD
#1712 opened by fborisovskii - 0
- 1
Documentation to add an MMIO device as a plugin
#1708 opened by Koceilito - 0
doubt with vector masking register instruction
#1706 opened by deepaannnavi - 1
Reading macro RD behave unexpected
#1707 opened by Lesliehsyu - 3
SSTC exception behavior
#1697 opened by JJ-Gaisler - 2
- 4
Legal ISA string option not accepted
#1696 opened by christian-herber-nxp - 2
Dynamic CSR read/write mask
#1692 opened by ved-rivos - 0
What time the spike will support the zjpm extension?
#1693 opened by yangye0212 - 1
issue in counting numbers of instructions
#1686 opened by Sanoj-S-Vijendra - 3
assert failed in vectorUnit.cc from 71line. T&vectorUnit_t::elt(reg_t,reg_t,bool)[with T=long unsigned int; reg_t=long unsigned int]: Assertion '(VLEN>>3)/sizeof(T)>0' failed.
#1685 opened by huihuiei - 8
fatal error: config.h: No such file or directory
#1683 opened by silabs-robin - 5
- 2
- 1
vmv1r.v instruction's behavior
#1680 opened by EventScheduler - 3
Facing Issue running Zvbb RVV Cryptography Instructions
#1676 opened by akifejaz - 3
Why misaligned store will raise store/amo access fault at the function store_slow_path?
#1668 opened by yangye0212 - 1
- 4
- 2
Zfa extension instruction fcvtmod_w_d behavior conflict with sail model on too large/ too small boundary
#1669 opened by GuoShibo-cn - 2
mstatus.fs cannot be written as initial
#1665 opened by omerguzelelectronicguy - 7