riscv/riscv-debug-spec

Clarification of register needed

CLappin opened this issue · 1 comments

Hi,

Apologies if this has been fixed already, I think there is either a typo or some context missing in Appendix 2, A.2. Execution Based, in the second paragraph:

"When taking this jump, is saved to dpc and cause is updated in dcsr. This jump is similar to a trap but it is not architecturally considered a trap, so for instance doesn’t count as a trap for trigger behavior."

Should it be something like:

"When taking this jump, register x is saved to dpc and cause is updated in dcsr. This jump is similar to a trap but it is not architecturally considered a trap, so for instance doesn’t count as a trap for trigger behavior."

Not sure which register should be "register x" here but it just reads off to me.

Thanks,
Ciaran

Another Asciidoc conversion problem. implementations.tex said:

When taking this jump, \Rpc is saved to \RcsrDpc and \FcsrDcsrCause is updated