What is a GC interrupt

[allenjbaum]

A GC interrupt is not defined in the Risc-V privileged spec.
What causes it?
What is the mcause value set when the interrupt is taken?

[robfinch]

I’m not sure about the implementation details of a GC interrupt, but I’m assuming it would work like an external timer interrupt. It would be driven by a PIT. I feel it’s a little bit outside of the scope of the document to define the GC hardware as I think this could vary significantly based on the design. As I’ve got it setup in my system as a lower priority external hardware interrupt somewhere in the cause code range 32 to 47 (39 IIRC). It’s not in the RISCV spec I’m reading what causes code are used for what external hardware interrupts, other than it says that hardware interrupts set the MSB of the cause register. The rest of the bits are reserved. However, I use an eight-bit vector in the reserved bits for external hardware interrupts. The cause code is latched on a bus at the time the IRQ occurs. There are actually two GC interrupts planned in the system, the second interrupt is a time limit interrupt on the amount of GC processing taking place. The first interrupt triggers a timer for the second interrupt. When the second interrupt occurs GC operations are suspended. I suppose this could also be done with an instruction counter.

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