robseb/socfpgaPlatformGenerator

Question - generation of SPL image (preloader) for Cyclone V

filip-dahlberg opened this issue · 1 comments

filip-dahlberg commented

Hi robseb,

I'm in the process of using the socfpgaPlatformDesigner.py script for generating the SD image for Cyclone V.

I can see that the script has separate settings for the three Intel SoCs; Cyclone V, Arria V and Arria 10, regarding generation of SPL (preloader). I believe that I'll need to generate the SPL (preloader) image file since the SDRAM likely differs from the one that you are using in the default SPL file. Would you like to provide guidance reading what a developer like me need to set the "generate_spl_image_file" and "u_boot_bsp_qts_dir_list" to if the hardware peripherals differs from your designs?
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Run the bootloader filter script (Cyclone V)

Cyclone V | Arria V | Arria 10

run_filter_script =[True, True, False]
u_boot_bsp_qts_dir_list = ['/board/altera/cyclone5-socdk/qts/', '/board/altera/arria5-socdk/qts/',
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Generate the bootable SPL image file

Cyclone V | Arria V | Arria 10

generate_spl_image_file = [False,False,True]

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