Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, for decoupling board details from design sources.
- Physical Constraints File (
*.pcf) for Lattice IceCube2. - Lattice Preference File (
*.lpf) for Lattice Diamond. - User Constraint Files (
*.ucf) for Xilinx ISE ≤14.7. - Xilinx Design Constraints (
*.xdc) for Xilinx Vivado. - Synopsis Design Constraints (
*.sdc) for Altera Quartus-II. - Physical Design Constraint (
*.pdc) for Microsemi Libero-SoC.
For each board, provide a set of constraint files, according to the following rules:
- Split pin constrains from per IP core timing constrains.
- Spilt pin constrains per interface/connector (switches, LEDs, Ethernet, UART, etc.). This allows enabling/disabling interfaces by selecting which files to include.
- Prefix each port with the board name.
- If an interface is fixed, include matching timing constraints. E.g. a button with
set_false_path,system_clockwith 100 MHz, or GMII with the 2 ns delay.
- Define constraints in a YAML file with yet to be defined coding style rules.
- Write generators that export the content to vendor specific formats.
- Write importers that read existing vendor specific constraint files and generate a YAML file.
The recommended approach for using these constraints in an existing HDL design is to define one top level source per board, on top of the design's top unit. To avoid ambiguity, we name the former BoardTop and the latter DesignTop. The purpose of BoardTop is describing board specific resources (PLLs, DCMs, RAM controllers, etc.) and type/polarity conversions, so that the DesignTop is unmodified for either simulation or implementation, with any tool and/or target board.
Find examples in the following repositories:
PoC has a large collection of constraint files for Xilinx ISE/Vivado and Intel/Altera's Quartus-II. The initial commit of this repository imported most of the content from VLSI-EDA/PoC: ucf/.
fpga_lib contains some YAML files that use a custom format: INTI-CMNB-FPGA/fpga_lib: boards/. A Python script (boardfiles.py) allows generating UCF files from the YAML sources.
*.pcf and *.lpf files for open source boards were picked from vhdl-cfg, which are based on resources from ghdl/ghdl-yosys-plugin, antonblanchard/ghdl-yosys-blink, im-tomu/fomu-workshop, etc.
litex-boards is equivalent to this repository, but constraints are defined as Python modules. It'd be interesting to allow conversions between the YAML and LiteX board definitions. At the same time, from LiteX definitions it should be possible to generate vendor constraint files matching the guidelines.
yosys-symbiflow-plugins contains plugins for Yosys developed as part of the SymbiFlow project. Some of those plugins are the xdc-plugin or the sdc-plugin. Those take the constraints and information and converts them to annotations on RTL. Annotations can also be directly provided in HDL too. Hence, the aim is to collect everything into the RTL and then write the data back for downstream tools to use. The main benefit of this approach is using the names in RTL, instead of dealing with mangled names after optimisation. See also XDC commands supported by SymbiFlow Yosys Plugins and Yosys and Constraints System.
fusesoc proposes an open source YAML format for defining cores. Hence, the constrains provided in this repository are expected to be used in those core definition sources. Ideally, fusesoc might import the YAML definition, instead of defining different filesets for each tool.
The board data files used with Xilinx Vivado are hosted at Xilinx/XilinxBoardStore. The upstream of Xilinx/XilinxBoardStore: boards/Digilent/ is Digilent/vivado-boards.