RISC-V targets do not support ARM "thread mode" check
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Disasm commented
async-on-embedded/async-embedded/src/executor.rs
Lines 203 to 207 in 47eb470
This code checks for a value of the VECTACTIVE
field (only for bits 7..0 of the 9-bit field). This value corresponds to the current interrupt number handled (0 for none).
I wonder what should we use here for RISC-V. @ilya-epifanov any ideas?