Tracking Issue for `f16` and `f128` float types

@tgross35 we (rizinorg) have merged the changes on our demangling library. i have added also some tests https://github.com/rizinorg/rz-libdemangle/blob/main/test/test_rust.c#L75-L78

That was super fast :) the update is much appreciated.

Note that the mangling isn't actually finalized but does seem reasonably likely to merge as-is #122106

Answer 15 · 2024-04-01T08:00:58.000Z

i don't think that will be a big issue. i can always fix this once is merged if it ever changes.

Answer 16 · 2024-04-11T18:30:12.000Z

@wargio #122106 wound up being closed in favor of C3f16 and C4f128 (#123816), which should already demangle correctly. So I think you should be able to revert the addition. Sorry for the noise!

Answer 17 · 2024-04-12T04:39:50.000Z

@tgross35 i will. i read about the decision yesterday, so for me is just a couple of lines that needs to be removed. thank you for your wonderful work!

Answer 18 · 2024-06-13T15:42:31.000Z

arm64ec-pc-windows-msvc can't compile functions that pass or return f16 or f128 due to llvm/llvm-project#94434.

Answer 19 · 2024-06-13T21:26:00.000Z

More LLVM bugs:

Tier 2 s390x-unknown-linux-gnu doesn't support f16: llvm/llvm-project#50374
Tier 2 nvptx64-nvidia-cuda doesn't support f128: llvm/llvm-project#95471
Tier 3 sparc-unknown-linux-gnu doesn't support passing f128 directly (error message SPARCv8 does not handle f128 in calls; pass indirectly): llvm/llvm-project#41838

Answer 20 · 2024-06-23T15:37:01.000Z

64-bit MIPS targets (all tier 3) have a bug involving f128 that prevents compilation of compiler-builtins in debug mode without the no-f16-f128 feature: llvm/llvm-project#96432

Answer 21 · 2024-06-23T18:17:15.000Z

wasm32 (tier 2) has f16 bugs with failing to round in-between operations (llvm/llvm-project#96437) and quietening signalling NaNs in some situations when passing to and returning from a function (llvm/llvm-project#96438).

Answer 22 · 2024-07-08T03:02:41.000Z

It seems the LLVM f16 excess precision and ABI-handling bugs aren't limited to WASM:

The list of affected LLVM backends is included in each issue: both affect tier 2 and tier 3 Rust targets.

Answer 23 · 2024-07-10T19:28:41.000Z

The test suite currently fails on s390x in the following doctests:

    library/core/src/num/f16.rs - f16::f16::is_sign_negative (line 377)
    library/core/src/num/f16.rs - f16::f16::is_sign_positive (line 354)
    library/core/src/num/f16.rs - f16::f16::to_be_bytes (line 695)
    library/core/src/num/f16.rs - f16::f16::to_le_bytes (line 716)
    library/core/src/num/f16.rs - f16::f16::to_ne_bytes (line 743)

due to

rustc-LLVM ERROR: Cannot select: 0x3ffcc0737a0: i32 = fp_to_fp16 0x3ffcc072fc0

(which is llvm/llvm-project#50374)

After #127235 most doctests are already restricted to x64_64 (or aarch64), but these few listed above remain active on all Linux platforms. Could those also be restricted for now (until the s390x LLVM back-end is fixed) so that the test suite passes again? Thanks!

Answer 24 · 2024-07-10T20:04:20.000Z

Thanks for reporting @uweigand, yes those could be restricted too. Feel free to open a PR similar to #127235 if you're up for it, otherwise I'll try to put one up in the next couple days.

Answer 25 · 2024-07-10T21:25:31.000Z

Thanks for reporting @uweigand, yes those could be restricted too. Feel free to open a PR similar to #127235 if you're up for it, otherwise I'll try to put one up in the next couple days.

I've now opened #127588, thanks!

Answer 26 · 2024-07-10T21:30:01.000Z

LLVM lowers f16 FMA incorrectly on targets without native f16 FMA support (so this will affect most targets including all tier 1 targets): llvm/llvm-project#98389

Answer 27 · 2024-07-14T23:15:18.000Z

It appears that today f128 doesn't trigger the incomplete_features lint: https://play.rust-lang.org/?version=nightly&mode=release&edition=2021&gist=9d8a3698d5d506fc960bde270e9a1a54

It might be a good idea to do that for now, to avoid people making threads like https://users.rust-lang.org/t/display-for-f128/114405?u=scottmcm

Answer 28 · 2024-08-02T09:17:04.000Z

Tier 3 powerpc64-ibm-aix doesn't currently support f128 arguments: llvm/llvm-project#101545

Answer 29 · 2024-10-13T00:34:36.000Z

llvm/llvm-project#104915: f16 abs and neg quieten signalling NaNs on targets where f16 is not natively supported.

Answer 30 · 2024-11-17T09:29:39.000Z

Hurry up. I can't wait

Answer 31 · 2024-11-26T02:07:48.000Z

Warning: div_euclid and rem_euclid is buggy. I'm not sure whether they need be marked as unsafe, since calculate div/rem with floating types are strongly discouraged.

#![feature(f16, f128)]
fn main() {
    let a = 1.2f16;
    let b = 1.1f32;
    let c = 1.1f64;
    let d = 1.1f128;
    println!(
        "{} {} {} {}",
        (12f16).div_euclid(a) as f64,
        (11f32).div_euclid(b),
        (11f64).div_euclid(c),
        (11f128).div_euclid(d) as f64
    );
    println!(
        "{} {} {} {}",
        (12f16).rem_euclid(a) as f64,
        (11f32).rem_euclid(b),
        (11f64).rem_euclid(c),
        (11f128).rem_euclid(d) as f64
    );
}
// 10 10 10 10
// 1.1982421875 1.0999998 1.0999999999999992 1.1

Answer 32 · 2024-11-26T02:25:36.000Z

@Neutron3529: If you could, the thing to do would be to file a separate issue for that if there isn't one already. Reference this tracking issue in that new issue.

Tracking Issue for `f16` and `f128` float types

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