sahadipayan/System_Verilog_Assertion_to_RTL_Synthesizer
A synthesizer capable of transforming SVA properties into synthesizable hardware modules in Verilog register-transfer level (RTL).
PythonApache-2.0
No issues in this repository yet.
A synthesizer capable of transforming SVA properties into synthesizable hardware modules in Verilog register-transfer level (RTL).
PythonApache-2.0
No issues in this repository yet.