sanxzhar

sanxzhar's Stars

• I-S00N/I-S00N

  3.9k1.9k

• IS2AI/Kazakh_TTS

  An expanded version of the previously released Kazakh text-to-speech (KazakhTTS) synthesis corpus. In KazakhTTS2, the overall size has increased from 93 hours to 271 hours, the number of speakers has risen from two to five (three females and two males), and the topic coverage has been diversified.

  Language:Shell12425

• tynyshtyq/ultra

  ultra: a tool to track your academic performance | by dastan rinatuly

  Language:TypeScript2

• langchain-ai/langchain

  🦜🔗 Build context-aware reasoning applications

  Language:Jupyter Notebook97.3k15.8k

• mit-pdos/xv6-riscv

  Xv6 for RISC-V

  Language:C7.4k2.7k

• maybe-finance/maybe

  The OS for your personal finances

  Language:Ruby34.7k2.5k

• romkatv/powerlevel10k

  A Zsh theme

  Language:Shell47.2k2.2k

• chipsalliance/sv-tests

  Test suite designed to check compliance with the SystemVerilog standard.

  Language:SystemVerilog30575

• feature-sliced/documentation

  🍰 Architectural methodology for frontend projects

  Language:MDX1.6k175

• zed-industries/zed

  Code at the speed of thought – Zed is a high-performance, multiplayer code editor from the creators of Atom and Tree-sitter.

  Language:Rust52.2k3.3k

• rails/rails

  Ruby on Rails

  Language:Ruby56.3k21.7k

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k217

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3.1k578

• OpenTimer/Parser-Verilog

  A Standalone Structural Verilog Parser

  Language:Verilog8634

• davidkebo/verilog-parser

  A verilog parser

  Language:C176

• vnglst/pong-wars

  Language:HTML1.2k142

• mshr-h/vscode-verilog-hdl-support

  HDL support for VS Code

  Language:TypeScript30279

• jordan-cutler/path-to-senior-engineer-handbook

  All the resources you need to get to Senior Engineer and beyond

  14k1.3k

• TimRudy/uart-verilog

  A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

  Language:Verilog234

• utmapp/UTM

  Virtual machines for iOS and macOS

  Language:Swift27.6k1.4k

• Homebrew/homebrew-core

  🍻 Default formulae for the missing package manager for macOS (or Linux)

  Language:Ruby13.9k12.5k

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.6k627

• Shiyan7/kinomore-v2

  Large project on the effector/fsd stack

  Language:TypeScript11321

• microsoft/vscode

  Visual Studio Code

  Language:TypeScript166k29.9k

• rasbt/LLMs-from-scratch

  Implement a ChatGPT-like LLM in PyTorch from scratch, step by step

  Language:Jupyter Notebook36.7k4.7k

• TanStack/query

  🤖 Powerful asynchronous state management, server-state utilities and data fetching for the web. TS/JS, React Query, Solid Query, Svelte Query and Vue Query.

  Language:TypeScript43.2k3k

• kabylkas/elce202labs

  The labs based on Intel's Academic Program lab exercise material.

  1

• t3-oss/init.tips

  Language:Astro21019

• ashishps1/awesome-system-design-resources

  Learn System Design concepts and prepare for interviews using free resources.

  Language:Java19.3k4.7k

• RamboXD/ReactivePhoenix

  React + Phoenix

  Language:Elixir2