Problems connect dut entity to bus

[RasmusGOlsen]

I have problems understanding the documentation on how to connect the dut entity to the bus. I have these signals on the dut object.

entity spi_master is
   port (
      spi_miso       : in  std_logic;
      spi_mosi       : out std_logic;
      spi_clk        : out std_logic;
      spi_cs_n       : out std_logic_vector(7 downto 0)
   );
end;

I have tried several ways but are still not able to get it correct.

spi_bus = SpiBus.from_prefix(dut, "spi", sclk_name="clk", cs_name="cs_n[0]")

spi_bus = SpiBus(
    signals={
        'sclk': dut.spi_clk,
        'mosi': dut.spi_mosi,
        'miso': dut.spi_miso,
        'cs': dut.spi_cs_n[0]
    }
)

[schang412]

Hi, this extension currently does not support multi-bit chip select. I would recommend writing a wrapper for testing so that the chip select is a single bit.

There may be room for improvement in the extension by allowing certain signals to be passed in as a dictionary as you demonstrate.