This repository is read-only as most of its contents were upstreamed to Chisel in chipsalliance/chisel#3199. Please direct improvements to upstream Chisel.
This repository contains experimental software that enables separable compilation in Chisel.
This repository seeks to answer questions related to:
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What is the interface between separately compiled Chisel modules?
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How to define a stable port-level interface between Chisel modules?
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How can information, other than ports, be included in an interface?
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What information can be passed between separable compilation units?
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How can information that requires an interface implementation be described and communicated?
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What software patterns are applicable to this problem?