sergeykhbr/riscv_vhdl

Issues

• Any plans or suggestions for laticce or gowin fpga chips support?

  #47 opened a year ago by nerfur
  1

• riscv_soc_tb Simulaton

  #44 opened a year ago by Youssef-IA
  18

• Adding a Master peripheral

  #45 opened 2 years ago by Mina2411
  27

• simulation of kc705_tb

  #46 opened a year ago by mito200
  19

• Run Hello world example on VC707 board

  #43 opened a year ago by Mina2411
  24

• slurm dependency

  #42 opened 2 years ago by ejessen
  3

• can you run linux?

  #36 opened 2 years ago by rafaelcorsi
  2

• problem compilation with options: -march=rv64imafd -DFPU_ENABLED

  #37 opened 2 years ago by bitprog10
  1

• Communicating with the ML605 Board (v8.0)

  #35 opened 2 years ago by gutkedu
  4

• How to generate VCD files of bare-metal dhrystone with _run_systemc_sim.sh?

  #41 opened 3 years ago by cnjsdfcy
  4

• Build debugger with GUI failed: libdbg64g.so undefined reference

  #40 opened 3 years ago by HollaHieu
  1

• GNSS module

  #38 opened 4 years ago by mfkiwl
  1

• gptimer alignment in the second timer is not correct

  #33 opened 5 years ago by hossameldin1995
  2

• Uart Conf

  #31 opened 5 years ago by suhasskrishanmurthy
  1

• Openning ttyUSB0 at 115200 . . .failed"

  #29 opened 5 years ago by suhasskrishanmurthy
  3

• Generating bit file for boot up using debugger

  #30 opened 5 years ago by taniyagarg4
  5

• Error compiling debugger

  #32 opened 5 years ago by FrankAnze
  1

• showing CPU is turned off

  #28 opened 5 years ago by suhasskrishanmurthy
  1

• Cannot find _run_functional_sim.sh

  #27 opened 5 years ago by suhasskrishanmurthy
  2

• What configuration did you use for Rocket core?

  #26 opened 5 years ago by teadotjay
  2

• Zynq-7000

  #25 opened 5 years ago by racarla
  2

• freertos port for river core

  #24 opened 5 years ago by suhasskrishanmurthy
  3

• Do you plan to write FPU for River CPU?

  #23 opened 6 years ago by hyf6661669
  1

• Problems with building (or rather starting) the debugger

  #22 opened 6 years ago by nils1603
  1

• Potential ICache Bug

  #19 opened 6 years ago by mateoconlechuga
  6

• A few questions

  #15 opened 6 years ago by mateoconlechuga
  5

• riscv_soc_tb crashes in Vivado Simulator

  #18 opened 6 years ago by mateoconlechuga
  2

• loadelf is not working

  #17 opened 6 years ago by southlife
  4

• Boot procedure bypass ROM FW copy to SRAM

  #16 opened 6 years ago by daffy1108
  3

• How to build River CPU?

  #14 opened 6 years ago by mateoconlechuga
  3

• MMU Support?

  #13 opened 6 years ago by mateoconlechuga
  2

• missing packages?

  #12 opened 6 years ago by mattdaehn
  2

• elf2raw64 и .shstrab

  #11 opened 7 years ago by kraziant
  6

• how to generate bitstream file by myself ?

  #9 opened 7 years ago by gobs-code
  11

• Generate failed of helloworld hex file

  #8 opened 7 years ago by gobs-code
  2

• Will this fit on an Avnet S6microboard (Spartan6 LX9)

  #7 opened 7 years ago by salmansheikh
  1

• compiling errors

  #6 opened 7 years ago by gobs-code
  2

• Rtos port on RISC-V

  #5 opened 7 years ago by ninode
  3

• The software models with GUI closes automatically

  #4 opened 8 years ago by satya123bora
  2

• Building bootimage fails on linux using riscv-gcc 5.3.0

  #2 opened 9 years ago by bkoppelmann
  1

• Bare-metal Rocket Chip

  #1 opened 9 years ago by pbn4
  1