rcr not setting cf to true

[brandonros]

[
  {
    "i": 2968,
    "iHex": "b98",
    "x64dbgLine": {
      "rawLine": {
        "Index": "00B98",
        "Address": "0000000144EC1D68",
        "Bytes": "81DB 335E463C",
        "Disassembly": "sbb ebx,3C465E33",
        "Registers": "rbx: FFFFFFFFFFFFC81D-> C3B969E9",
        "Memory": "",
        "Comments": ""
      },
      "rip": "144ec1d68",
      "registerChanges": [
        {
          "registerName": "rbx",
          "previousValue": "ffffffffffffc81d",
          "newValue": "c3b969e9"
        }
      ],
      "memoryChanges": []
    },
    "scemuLine": {
      "rawLine": {
        "diffRegLine": "diff_reg: pos = 2968 rip = 144ec1d68 rbx ffffffffffffc81d -> c3b969ea;",
        "memTraceLines": []
      },
      "position": "b98",
      "rip": "144ec1d68",
      "registerChanges": [
        {
          "registerName": "rbx",
          "previousValue": "ffffffffffffc81d",
          "newValue": "c3b969ea"
        }
      ],
      "memoryChanges": []
    },
    "instructionErrors": [
      {
        "index": 0,
        "message": "newValue mismatch",
        "x64dbg": "c3b969e9",
        "scemu": "c3b969ea"
      }
    ]
  },

[brandonros]

https://www.felixcloutier.com/x86/sbb

[brandonros]

[brandonros]

2969 0x144ec1d68: sbb   ebx,3C465E33h
	diff_flags: pos = 2968 rip = 144ec1d68 in = 202 out = 282 f_sf 0 -> 1; 
	diff_reg: pos = 2968 rip = 144ec1d68 rbx ffffffffffffc81d -> c3b969ea; 
	rax: 0xfffffffffff63e25 rbx: 0xc3b969ea rcx: 0x144fa54ec rdx: 0x144fa54ec rsi: 0x14f490 rdi: 0x144e4713f rbp: 0x144ec1d56 rsp: 0x14f290
	r8: 0x50 r9: 0x14f480 r10: 0x8cb75dbe12d3c81d r11: 0x9d46c36de8c1ca8a r12: 0x1448a76a4 r13: 0x0 r14: 0x140000000 r15: 0x0
	r8u: 0x0 r9u: 0x0 r10u: 0x8cb75dbe r11u: 0x9d46c36d r12u: 0x1 r13u: 0x0 r14u: 0x1 r15u: 0x0
	r8d: 0x50 r9d: 0x14f480 r10d: 0x12d3c81d r11d: 0xe8c1ca8a r12d: 0x448a76a4 r13d: 0x0 r14d: 0x40000000 r15d: 0x0
	r8w: 0x50 r9w: 0xf480 r10w: 0xc81d r11w: 0xca8a r12w: 0x76a4 r13w: 0x0 r14w: 0x0 r15w: 0x0
	r8l: 0x50 r9l: 0x80 r10l: 0x1d r11l: 0x8a r12l: 0xa4 r13l: 0x0 r14l: 0x0 r15l: 0x0
	zf: false pf: false af: false of: false sf: true df: false cf: false tf: false if: true nt: false

[brandonros]

scemu

zf: false pf: false af: false 
of: false sf: true df: false 
cf: false tf: false if: true 
nt: false

x64dbg

[brandonros]

we should have of true by the time we get into this instruction

we also need cf true and tf true

let's see if i need to track these down or not

[brandonros]

B96 | 0000000144EC1D5F     | D3DB                     | rcr ebx,cl                              | rbx: FFFFFFFFFFFA |                                                                                          |

sets CF to true

ebx = 00000000FFFAD93F, cl = 00000000000000EC

[brandonros]

2966 0x144ec1d5f: rcr   ebx,cl
	diff_flags: pos = 2965 rip = 144ec1d5f in = 282 out = 202 f_sf 1 -> 0; 
	diff_reg: pos = 2965 rip = 144ec1d5f rbx fffffffffffad93f -> 27efffad; 
	rax: 0xfffffffffff63e25 rbx: 0x27efffad rcx: 0x144fa54ec rdx: 0x144fa54ec rsi: 0x14f490 rdi: 0x144e4713f rbp: 0x144ec1d56 rsp: 0x14f290
	r8: 0x50 r9: 0x14f480 r10: 0x14dd1f r11: 0x9d46c36de8c1ca8a r12: 0x1448a76a4 r13: 0x0 r14: 0x140000000 r15: 0x0
	r8u: 0x0 r9u: 0x0 r10u: 0x0 r11u: 0x9d46c36d r12u: 0x1 r13u: 0x0 r14u: 0x1 r15u: 0x0
	r8d: 0x50 r9d: 0x14f480 r10d: 0x14dd1f r11d: 0xe8c1ca8a r12d: 0x448a76a4 r13d: 0x0 r14d: 0x40000000 r15d: 0x0
	r8w: 0x50 r9w: 0xf480 r10w: 0xdd1f r11w: 0xca8a r12w: 0x76a4 r13w: 0x0 r14w: 0x0 r15w: 0x0
	r8l: 0x50 r9l: 0x80 r10l: 0x1f r11l: 0x8a r12l: 0xa4 r13l: 0x0 r14l: 0x0 r15l: 0x0
	zf: false pf: false af: false of: false sf: false df: false cf: false tf: false if: true nt: false

[sha0coder]

the new implementation of RCR is enabling CF,
OF should be true also?

--- flags ---
0x282
cf: false
pf: false
af: false
zf: false
sf: true
tf: false
if: true
df: false
of: false
iopl1: false
iopl2: false
nt: false
rf: false
vm: false
ac: false
vif: false
vip: false
id: false
---
=>
2966 0x144ec1d5f: rcr   ebx,cl
=>f
--- flags ---
0x287
cf: true
pf: true
af: false
zf: false
sf: true
tf: false
if: true
df: false
of: false
iopl1: false
iopl2: false
nt: false
rf: false
vm: false
ac: false
vif: false
vip: false
id: false
---

[brandonros]

fixed