shreyas1998
ECE Graduate | Interested in computer architecture | Hardware accelerators for machine learning
UT AustinAustin
shreyas1998's Stars
lirui-shanghaitech/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
MingSun-Tse/Efficient-Deep-Learning
Collection of recent methods on (deep) neural network compression and acceleration.
ddbourgin/numpy-ml
Machine learning, in numpy
mit-han-lab/proxylessnas
[ICLR 2019] ProxylessNAS: Direct Neural Architecture Search on Target Task and Hardware
google/CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
satwikkansal/wtfpython
What the f*ck Python? 😱
NNgen/nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
activeloopai/deeplake
Database for AI. Store Vectors, Images, Texts, Videos, etc. Use with LLMs/LangChain. Store, query, version, & visualize any AI data. Stream data in real-time to PyTorch/TensorFlow. https://activeloop.ai
Avnet/Ultra96-PYNQ
Board files to build Ultra 96 PYNQ image
akilm/Physical-Design
Physical Design Flow from RTL to GDS using Opensource tools.
damdoy/ice40_ultraplus_examples
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
pku-liang/FlexTensor
Automatic Schedule Exploration and Optimization Framework for Tensor Computations
bluespec/Piccolo
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
UCLA-VAST/FlexCNN
halide/Halide
a language for fast, portable data-parallel computation
vortexgpgpu/vortex
merrymercy/awesome-tensor-compilers
A list of awesome compiler projects and papers for tensor computation and deep learning.
BrunoLevy/learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
YosysHQ/fpga-toolchain
Multi-platform nightly builds of open source FPGA tools
fpga-opencl-benchmarks/rodinia_fpga
Rodinia Benchmark Suite for OpenCL-based FPGAs
ultraembedded/FPGAmp
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
altuSemi/Cores-biriscv-AltuSOC
FuseSoC-based SoC for SweRV EH1
skyzh/RISCV-Simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
Arlet/verilog-65C02-microcode
65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface
Xilinx/Vitis-HLS-Introductory-Examples
Xilinx/ResNet50-PYNQ
Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
RTimothyEdwards/qflow
Qflow full end-to-end digital synthesis flow for ASIC designs
RalphMao/EIE-simulator
C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)
huawei-noah/bolt
Bolt is a deep learning library with high performance and heterogeneous flexibility.
luigifreda/pyslam
pySLAM contains a monocular Visual Odometry (VO) pipeline in Python. It supports many modern local features based on Deep Learning.