shreyasnbhat/vliw-architecture

Implement Control Circuit for Single Cycle VLIW

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shreyasnbhat commented
  • Implement Control Ckt for the Single Cycle Datapath.
  • Implement singleCycle module in cache.v file.
  • Write tesbench to test results against IM instruction add $3 ,$1,$2 || c.and $4,$5