sifive/duh

Issues

• relax validation

  #91 opened a year ago by mrwinsto
  0

• repetitive sets of items

  #90 opened a year ago by drom
  0

• report status of DUH document

  #67 opened 5 years ago by drom
  10

• replace master/slave -> initiator/target

  #79 opened 5 years ago by drom
  1

• clean all unused references in the definition section

  #27 opened 6 years ago by drom
  1

• duh validate doesn't find custom buses

  #59 opened 5 years ago by olofk
  2

• DuH Validate Returns Zero Exit Code on Validation Failure

  #86 opened 4 years ago by seldridge
  1

• DuH validate not handling verbose port definitions

  #87 opened 4 years ago by seldridge
  0

• Design option in "Block Type" doesn't create any (.json5) base document

  #85 opened 4 years ago by adeelliaquat-lm
  2

• No module named 'cvxopt'

  #83 opened 4 years ago by davidmlw
  1

• tick-define macro substituted with incorrect value in json5

  #33 opened 6 years ago
  1

• inout verilog import - width missing

  #58 opened 4 years ago by drom
  4

• duh validate prints out unnecessary validation errors when DUH document not passed in

  #66 opened 4 years ago by richardxia
  2

• duh validate doesn't work with absolute paths.

  #81 opened 4 years ago by rpadler
  3

• duh validate issues a warning on bundles

  #72 opened 4 years ago by Ramlakshmi3733
  1

• Default value of access/modifiedWriteValue/readAction properties

  #80 opened 5 years ago by taichi-ishitani
  2

• duh validate should disallow duplicate address block names

  #78 opened 5 years ago by richardxia
  3

• "component" is spelled wrong in validate command

  #77 opened 5 years ago by mwachs5
  0

• think about linking programming interface to register description to bus interface

  #76 opened 5 years ago by drom
  0

• component, busInterface, portMap, port concatenation

  #74 opened 5 years ago by drom
  0

• detect type of the document

  #75 opened 5 years ago by drom
  0

• https://duh.run website broken

  #65 opened 5 years ago by mithro
  3

• warning about unmapped ports (component)

  #73 opened 5 years ago by drom
  0

• component -> busInterface -> port -> presence ('optional' by default)

  #71 opened 5 years ago by drom
  0

• duh get the root document

  #70 opened 5 years ago by drom
  0

• use duh-core

  #69 opened 5 years ago by drom
  0

• Clarify README quickstart instructions regarding `duh` executable path

  #64 opened 5 years ago by richardxia
  0

• Fetch $ref files

  #62 opened 5 years ago by drom
  0

• cascading attributes: memoryMap -> register -> field

  #63 opened 5 years ago by drom
  0

• duh validate returns 0 even if error is found

  #60 opened 5 years ago by jackkoenig
  0

• Create a Python library for working with DUH?

  #56 opened 5 years ago by mithro
  4

• CLIi to validate parameters against component parameter schema

  #57 opened 5 years ago by drom
  0

• duh-design

  #55 opened 6 years ago by hiren-99
  0

• duh-import-verilog-ports isuue

  #51 opened 6 years ago by hiren-99
  3

• import IP-XACT ports and SYSTEMRTL ports

  #53 opened 6 years ago by hiren-99
  1

• Import memory map of verilog to json5.

  #52 opened 6 years ago by hiren-99
  0

• request for field to substitute different name for blackbox and block name

  #50 opened 6 years ago
  0

• Duh import verilog ports issue

  #47 opened 6 years ago by v-krvavac
  3

• validate port interfaces mapped to existing ports

  #49 opened 6 years ago by drom
  0

• Validate Bus Interfaces against Bus Definitions

  #48 opened 6 years ago by drom
  0

• Can't map parts of signals in duh

  #40 opened 6 years ago by v-krvavac
  0

• Verilog to json5

  #23 opened 6 years ago by shiviarorasifive
  3

• Travis CI failing on Windows

  #36 opened 6 years ago by drom
  0

• Travis CI failing on OSX

  #35 opened 6 years ago by drom
  0

• verilog macro flagged as syntax error

  #31 opened 6 years ago
  5

• pinlist empty if blank line after module module_name (

  #30 opened 6 years ago
  3

• Issue in importing verilog ports to json5

  #28 opened 6 years ago by sidharth94
  2

• use duh schema from duh-schema

  #24 opened 6 years ago by drom
  2

• duh-export-verilog-bbx CLI

  #26 opened 6 years ago by drom
  0

• How is mycom-busprop.json supposed to be interpreted/used?

  #22 opened 6 years ago
  1