General RAM issue

Question

General RAM issue

Closed this issue 3 years ago · 2 comments

Mostly one byte is routed on few layers. It should be on one.

UG583:
DQ and DQS signals in the same byte group should be routed in the same layer from UltraScale device to DRAM/DIMM, except in the breakout areas. Include the data mask (DM) in the byte group as applicable.

Answer 1 · 2021-06-28T15:43:36.000Z

As current design has passed all RAM simulation tests, I think that it's not worth changing the layout.

Answer 2 · 2021-07-04T21:15:02.000Z

In general I dislike it. But since Altium count delays and simulation passes it may be right.