Issues
- 5
Question on Evaluating Staq
#46 opened by khieta - 0
- 3
Inliner does not inline conditioned gates
#76 opened by p51lee - 1
- 5
JSON parse issue for device mapping
#66 opened by manavbabel - 4
- 1
Oracle synthesis: verilog array format?
#48 opened by gribeill - 1
Bugs in benchmarks
#47 opened by khieta - 0
Mismatch issues of the rz
#45 opened by vsoftco - 6
- 3
Python interface
#30 opened by yourball - 2
A minor problem?
#33 opened by DevelopDaily - 1
Wiki's usage help does not match with program's
#40 opened by WATLE - 12
Phases of the final states shifted
#34 opened by DevelopDaily - 1
Does the Openqasm compiler support OpenQASM 3?
#39 opened by moar55 - 1
OpenQASM->ProjectQ minor issues
#38 opened by vsoftco - 2
Optimization by self-annihilating sequences
#37 opened by DevelopDaily - 1
Port travisCI to CircleCI
#35 opened by vsoftco - 4
- 1
Bug Report: staq hangs with these arguments
#31 opened by DevelopDaily - 2
Mapping: steiner vs swap - 100 times slower
#29 opened by DevelopDaily - 2
- 2
- 2
- 17
Output qubit mapping information
#20 opened by meamy - 3
A simple test case to address a potential issue of desugaring the barrier gate
#12 opened by DevelopDaily - 1
Reopened: Failed to parse floating-point numbers in scientific notation form (OpenQASM)
#25 opened by DevelopDaily - 2
Bug report: // comment vs. //comment
#22 opened by DevelopDaily - 3
- 2
- 1
A bug? Oracle from Verilog.
#21 opened by DevelopDaily - 1
- 5
- 1
Bug report: CX gate on the same qubit
#17 opened by DevelopDaily - 1
- 1
"if statement" - looks like a bug.
#15 opened by DevelopDaily - 2
barrier on classical bits
#14 opened by DevelopDaily - 3
- 1
A simple test case to reveal a potential bug
#10 opened by DevelopDaily - 2
- 2
- 5
Error: libc++abi.dylib: terminating with uncaught exception of type std::logic_error: No indices left to pivot on, but multiple vectors remain!
#7 opened by Aerylia - 2
- 3
- 0
Cirq output error for NamedQubit
#3 opened by amccaskey - 6