/EQ

pipelined SPDIF decoder and equalizer. verilog modules and tb's

Primary LanguageVerilog

This code is more of a historical artefact from a job interview. Certain components may function, yet no guarantees are provided overall.

S/PDIF to PCM converter, with band equalizer in-between.

Input clock is 384xFs (Fs - samples freq) = 18.432 MHz. Samples are 48 kHz, 24 bits.