splade

splade's Stars

• golang-standards/project-layout

  Standard Go Project Layout

  Language:Makefile49.6k5871095.2k

• coollabsio/coolify

  An open-source & self-hostable Heroku / Netlify / Vercel alternative.

  Language:PHP34.6k1121.9k1.9k

• AmruthPillai/Reactive-Resume

  A one-of-a-kind resume builder that keeps your privacy in mind. Completely secure, customizable, portable, open-source and free forever. Try it out today!

  Language:TypeScript25.9k1161.4k2.6k

• nrwl/nx

  Smart Monorepos · Fast CI

  Language:TypeScript23.8k16610.6k2.4k

• wulkano/Kap

  An open-source screen recorder built with web technology

  Language:TypeScript18.1k175805827

• TransformerOptimus/SuperAGI

  <⚡️> SuperAGI - A dev-first open source autonomous AI agent framework. Enabling developers to build, manage & run useful autonomous agents quickly and reliably.

  Language:Python15.5k1754091.9k

• apitable/apitable

  🚀🎉📚 APITable, an API-oriented low-code platform for building collaborative apps and better than all other Airtable open-source alternatives.

  Language:TypeScript13.3k971.1k1.2k

• tinacms/tinacms

  A fully open-source headless CMS that supports Markdown and Visual Editing

  Language:TypeScript12k672k611

• vercel/commerce

  Next.js Commerce

  Language:TypeScript11.5k1835544.2k

• oramasearch/orama

  🌌 A complete search engine and RAG pipeline in your browser, server or edge network with support for full-text, vector, and hybrid search in less than 2kb.

  Language:TypeScript8.7k40259294

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala4.9k87415665

• roc-lang/roc

  A fast, friendly, functional language.

  Language:Rust4.5k1112.6k315

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.2k168176760

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3k97829571

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.9k134721531

• WAVM/WAVM

  WebAssembly Virtual Machine

  Language:C++2.7k74232226

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k229431k

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k9440286

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.7k88170419

• gem5/gem5

  The official repository for the gem5 computer-system architecture simulator.

  Language:C++1.7k733501.2k

• ZipCPU/zipcpu

  A small, light weight, RISC CPU soft core

  Language:Verilog1.3k6228157

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.3k3519344

• jordihales/hypercolor

  A curated collection of beautiful premade gradients using default colors from the Tailwind palette as well as a selection of custom color gradients.

  Language:Vue66482133

• f0rki/mapping-high-level-constructs-to-llvm-ir

  A guide that explains how high level programming language constructs are mapped to the LLVM intermediate language.

  Language:LLVM601223463

• IHP-GmbH/IHP-Open-PDK

  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

  Language:HTML4132911765

• NJU-ProjectN/nvboard

  NJU Virtual Board

  Language:C++23641551

• rq2e/rq2e

  Full source code for all examples and exercises in React Quickly, Second Edition – published by Manning Publications.

  Language:JavaScript714133

• grantae/OpenMIPS

  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions, over 100 hw/sw tests, and full ISA compliance

  Language:Assembly632113

• microdynamics-cpu/tree-core-cpu

  :deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

  Language:Scala36603

• montedalrymple/yrv

  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

  Language:Verilog173020