splade

splade's Stars

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.5k1381.8k895

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.2k168176760

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3k97829570

• morrownr/USB-WiFi

  USB WiFi Adapter Information for Linux

  2.8k65373179

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k229431k

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.6k723.6k614

• SpinalHDL/VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  Language:Assembly2.5k102334420

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k9440286

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.7k88170419

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k48961214

• ZipCPU/zipcpu

  A small, light weight, RISC CPU soft core

  Language:Verilog1.3k6128157

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k39122267

• NJU-ProjectN/nemu

  NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching

  Language:C8991866195

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog8685157275

• lnis-uofu/OpenFPGA

  An Open-source FPGA IP Generator

  Language:Verilog84043446162

• Trepan-Debuggers/remake

  Enhanced GNU Make - tracing, error reporting, debugging, profiling and more

  Language:C797517375

• Mathics3/mathics-core

  An open-source Mathematica. This repository contains the Python modules for WL Built-in functions, variables, core primitives, e.g. Symbol, a parser to create Expressions, and an evaluator to execute them.

  Language:Python7801415545

• lvyufeng/step_into_mips

  一步一步写MIPS CPU

  Language:Verilog750182155

• black-parrot/black-parrot

  A Linux-capable RISC-V multicore for and by the world

  Language:SystemVerilog62724412181

• YosysHQ/apicula

  Project Apicula 🐝: bitstream documentation for Gowin FPGAs

  Language:Verilog495378667

• dalance/svls

  SystemVerilog language server

  Language:Rust467104431

• IHP-GmbH/IHP-Open-PDK

  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

  Language:HTML4132911765

• OSCC-Project/iEDA

  Language:C++3244733

• SpinalHDL/NaxRiscv

  Language:Scala2692511240

• mirror/make

  git://git.savannah.gnu.org/make

  Language:C20316781

• USTC-System-Courses/CECS-Lab

  Language:C310011

• jgraph/drawio

  draw.io is a JavaScript, client-side editor for general diagramming.

  Language:JavaScript2423.7k8

• montedalrymple/yrv

  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

  Language:Verilog173020

• jaytlang/xv6-2020

  2020 6.S081 labs, on my own time

  Language:C20

• jaytlang/xv6-riscv

  Xv6 for RISC-V

  Language:C100