Set of MIPS assembly programs to help us find a secret cache configuration (cache size, block size and associativity) in both Data and Program cache. The expected cache size is 8KB, 16KB or 32KB, the block size range is from 4 up to 64 words per block and the associativity degree range is from 1 up to 8.
We used the QtMips simulator to simulate the cache.
More details of the implemention can be found in README.pdf (greek-only currently).