Where is the grammar parsing done?

[arunpatro]

Hi,

This is more of a question than an issue.

I want to verify the syntax correctness of a verilog code. How can I use iverilog to parse this?

How does iverilog parse the official verilog grammar ? I want to use the code version of verilog grammar in EBNF:

https://github.com/circuitgraph/circuitgraph/blob/main/circuitgraph/parsing/verilog.lark
https://www.verilog.com/VerilogBNF.html

[martinwhitaker]

You can't use iverilog to just parse the code, it will always perform elaboration as well unless it finds an error during parsing. But you can disable code generation and output, which saves quite a bit time on big designs, by

iverilog -t null -o /dev/null <source files>

You could force an error at the end of parsing by specifying an invalid top level module name with the -s option. You can prevent missing modules being treated as errors with the -i option.

The parser for iverilog is automatically generated by the GNU bison tool. Look in parse.y to see how the grammar is specified for this tool.

I'll move this to the Discussions area.