Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855

[1353369570]

Version
Yosys 0.39，yosys 0.40

On which OS did this happen?
Linux

Reproduction Steps
my test :

module top
(y, clk, wire197, wire196, wire195, wire194);
output wire [(32'h6e4):(32'h0)] y;
input wire [(1'h0):(1'h0)] clk;
input wire signed [(4'hd):(1'h0)] wire197;
input wire signed [(5'h10):(1'h0)] wire196;
input wire signed [(3'h6):(1'h0)] wire195;
input wire [(4'hd):(1'h0)] wire194;
reg signed [(5'h14):(1'h0)] reg204 = (1'h0);
reg [(5'h15):(1'h0)] reg203 = (1'h0);
reg [(5'h13):(1'h0)] reg202 = (1'h0);
reg [(3'h7):(1'h0)] reg201 = (1'h0);
reg [(4'hc):(1'h0)] forvar200 = (1'h0);
reg [(5'h13):(1'h0)] reg199 = (1'h0);
reg signed [(5'h13):(1'h0)] forvar198 = (1'h0);
assign y = {reg204,
reg203,
reg202,
reg201,
forvar200,
reg199,
forvar198,
(1'h0)};
always
@(posedge clk) begin
for (forvar198 = (1'h0); (forvar198 < (1'h1)); forvar198 = (forvar198 + (1'h1)))
begin
reg199 = wire196[(3'h6):(3'h4)];
for (forvar200 = (1'h0); (forvar200 < (2'h2)); forvar200 = (forvar200 + (1'h1)))
begin
reg201 = (&((^$unsigned($signed(reg199))) ?
$unsigned(((^forvar200) & (8'h9f))) : wire195));
reg202 <= (&$signed({($unsigned(forvar198) ?
$unsigned((7'h41)) : "x"),
("x" ? "" : $unsigned(reg201))}));
reg203 = (wire195[(1'h0):(1'h0)] == ((^{$signed(reg199),
(wire196 ? reg199 : wire197)}) ?
(-$unsigned((^forvar200))) : (~^(reg202[(2'h3):(1'h0)] <<< $unsigned(wire197)))));
reg204 <= $signed($unsigned($unsigned(wire196)));
end
end
end
endmodule
Expected Behavior
Like Vivado,yosys should successfully finished Verilog frontend.

Actual Behavior

[martinwhitaker]

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