suyash-20

Pinned Repositories

advent_of_code
Language:Python00
Arty-A7-35-XADC
Language:Verilog00
book_management
Language:Python00
bootstrap_blog_website
00
c-
Language:C++0 0 00
Computer-Organization-and-Architecture-LAB
Solution to COA LAB Assgn, IIT Kharagpur
Language:Verilog00
cpp-cheatsheet
Modern C++ Cheatsheet
Language:C++00
Python_repo
Language:Python00
SystemVerilog_repo
Language:SystemVerilog00
Verilog_Repo
Language:Verilog00

suyash-20's Repositories

suyash-20/advent_of_code
Language:Python00
suyash-20/Arty-A7-35-XADC
Language:Verilog00
suyash-20/book_management
Language:Python00
suyash-20/bootstrap_blog_website
00
suyash-20/c-
Language:C++0 0 00
suyash-20/Computer-Organization-and-Architecture-LAB
Solution to COA LAB Assgn, IIT Kharagpur
Language:Verilog00
suyash-20/cpp-cheatsheet
Modern C++ Cheatsheet
Language:C++00
suyash-20/Python_repo
Language:Python00
suyash-20/SystemVerilog_repo
Language:SystemVerilog00
suyash-20/todo-list
Language:HTML00
suyash-20/Verilog_Repo
Language:Verilog00
suyash-20/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog
suyash-20/esp-who
Face detection and recognition framework
Language:C
suyash-20/fifo
Language:SystemVerilog
suyash-20/fpga
The USRP™ Hardware Driver FPGA Repository
Language:Verilog
suyash-20/Introduction_signUp_form
suyash-20/profile_card_component
Language:HTML1 0
suyash-20/react-counter-app
Language:JavaScript
suyash-20/react-quiz
Language:TypeScript
suyash-20/redux-practice-counter
Language:JavaScript
suyash-20/RISC-V_RV32I
Language:Verilog
suyash-20/SignUpForm
1 0
suyash-20/SimpleCPU
An open source CPU design and verification platform for academia
Language:Verilog
suyash-20/SJSU_ROUTER_1x4
Language:JavaScript
suyash-20/Testinomials_grid_section
Language:HTML1 0
suyash-20/verilog-axi
Verilog AXI components for FPGA implementation