tharunchitipolu/RISC-V-32I-based-core-with-Advanced-Extensible-Interface
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
Verilog
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
Verilog