adder

Multiplier-Design

Telegram-Member-Adder

Python Member Adder For Telegram

flotadder

This is the VHDL code for a floating point adder

AddBot

سورس ربات ادد اجباری برای گروه تلگرام

VHDL-P4_Adder

Pentium 4 adder

SpiceAdders

A 16-bit carry skip adder and an unfinished Kogge-Stone adder.

verilog-assignments

Source code for various Verilog-based projects and assignments

SimpleBinaryCalculator

A Java binary calculator based on a system of gates

shock

A small package to manage logic circuits.

4-bit-Full-Adder-using-Verilog-HDL

Verilog code and testbench for 4-bit full adder

ksa

A synthesizable and modular Kogge-Stone Adder (KSA) implementation in SystemVerilog.

parallel-prefix-adder

A parallel-prefix adder implemented using Ling’s transformation.

FPU_Add_Unit_VHDL

In this project we have implemented Add/Minus unit and operations in a Floating-Point unit

VHDL_Adders

Different adders code in VHDL and Comparison

FPAM

Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.

PASS-2-4

A Diode-Transistor-Logic Adder System built from Scratch, with simplicity and robustness in mind

Carry_Lookahead_Adder

Designing a 4-bit Carry Lookahead Adder using eSim

adderlib

adderlib is an unofficial python wrapper for the Adder API for use with Adderlink KVM systems.

telkrap

Telegram scrapper auto adder, merger csv, and messager.

ACE203

Projects done in VHDL for course at ECE TUC. Used Xilinx Software either Vivado or ISE.

LicenseMe

🏷 Your handy tool for licensing and protecting your code.

digital-electronics-laboratory

Digital electronics is a field of electronics involving the study of digital signals and the engineering of devices that use or produce them.

FPGA-Design

FPGA design for implementing encoder, adder and counter circuits. (using logic tiles and switch boxes)

M9-VLSI-Anwendungen

Summary of projects I did in VLSI desing.

DigiAlpha

Optimized 32-Bit Full Adder, CEC-SAT Verifier & 2-SAT Solver

VHDL-DLX_ALU

ALU is the core of all operations, it elaborate two operands and performs logical and arithmetic operations based on the instruction passed to it by the CU.

Carry-Select-Adder

A carry select adder is an arithmetic combinational logic circuit which adds two N- bit binary numbers and outputs their N-bit binary sum and a 1-bit carry.

Quantum-Full-Adder

This is a full adder written in OpenQASM.

Full-Adder-Circuit-With-74LS157-74LS151-74LS153

➕➕ Arithmetic operations in most machines are performed in the ALU whereby logic gates and flipflops are combined so that they can subtract, multiply, and divide binary numbers. This circuit only implements the addition part, on four bit digits

lineageos_kernel_lenovo_a5000_nougat

KERNEL (3.10.108) For Lenovo A5000 (LOS14.1)

android_vendor_lenovo_a5000_adder_nougat

Lenovo A5000 (adder) - mt6582 - vendor files

android_device_lenovo_a5000_adder_nougat

Lenovo A5000 (adder) - mt6582 - device tree

CLA-vs-CRA

Compare the speeds of the Carry ripple adder and Carry-lookahead adder

BinaryAdder

A model to do binary addition

verilog-halfAdder

Hardware Simulation using Icarus Verilog EDA Playground for a half adder circuit design and test bench.