alu

There are 205 repositories under alu topic.

  • zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

    Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

    Language:Verilog1256333

  • bharathgs/NALU

    Basic pytorch implementation of NAC/NALU from Neural Arithmetic Logic Units paper by trask et.al

    Language:Python11514221

  • DoctorWkt/CSCvon8

    A crazy small 8-bit CPU built with only seventeen 7400-series chips.

    Language:Perl10416213

  • ghaiklor/nand-2-tetris

    Computer built from the ground up on top of own CPU, while compiler and assembler for it implemented in Rust language

    Language:Assembly75516

  • paranoiaproject/payuclient

    Payu ALU service client

    Language:PHP7217917

  • DoctorWkt/CSCv2

    Version 2 of my Crazy Small CPU

    Language:Perl675310
  • spam-1

    Johnlon/spam-1

    Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

    Language:Verilog65538

  • edson-acordi/4bit-microcomputer

    MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.

    Language:Python58552

  • RomeoMe5/DDLM

    Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

    Language:Verilog533042

  • smangul1/rop

    The Read Origin Protocol (ROP) is a computational protocol that aims to discover the source of all reads, including those originating from repeat sequences, recombinant B and T cell receptors, and microbial communities.

    Language:Shell3578614

  • timlg07/NandGame-Solutions

    Solutions for all levels of the NandGame.

    294106

  • princeofpython/Computer-Architecture

    Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

    Language:Verilog27316

  • goupaz/lowlevel

    Design your own CPU, Operating system, and Compiler (Maintainer: Emin Ghuliev)

    24903

  • clemgoub/TypeTE

    Genotyping of segregating mobile elements insertions

    Language:Perl19361

  • hoangsonww/Digital-Design-Labs

    🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.

    Language:Assembly1512010

  • mihir8181/VLSI-Design-Digital-System

    This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

    15106

  • Elidevin/nandgame.com-solutions

    Solutions for NandGame.com

    14102

  • AlexIII/R200

    R200 Relay Computer

    Language:C#13302

  • brilacasck/micro-acc-systemc

    simulating connection of micro processor and accelerator on a bus context with systemc language

    Language:C++13303

  • dominiksalvet/risc63

    Custom 64-bit pipelined RISC processor

    Language:VHDL13301

  • OpenBanboo/High-Performance-ALU

    RTL Design and Implementation of High Performance Algorithm Logic Units

    Language:Verilog13202

  • FaisalAhmedBijoy/SAP-1-Computer-Design-Logisim

    Simple As Possible (SAP) 1 Computer Design in Logisim

    10200

  • muhammadaldacher/Layout-Design-for-an-8-bit-Microprocessor

    Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS VLSI technology on Tanner EDA toolchain.

    10101

  • bananahell/OAC-RiscV

    Trabalho de Organização e Arquitetura de Computadores, UnB - 2020/2

    Language:VHDL8201

  • dominiksalvet/limen-alpha

    Dual-core 16-bit RISC processor

    Language:VHDL8402

  • Robin-WZQ/32bit-ALU

    32位ALU加法器（verilog），支持加法并行方式和真串行方式，6种运算（算术运算和逻辑运算），能够输出结果和4个标志位。

    Language:Verilog8101

  • luk3Sky/Building-A-Processor---Project

    Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

    Language:Verilog7101

  • SravanChittupalli/8-bit-ALU-in-verilog

    8-bit ALU in Verilog.

    Language:HTML7215
  • robin

    varkenvarken/robin

    SoC design targeted at the IceBreaker board

    Language:Assembly7200

  • bioinfo-ut/AluMine

    Scripts for discovery and genotyping polymorphic Alu element insertions in human genomes

    Language:Perl6212

  • elbekka/Programacion-De-Hardware-VHDL

    4 bits ALU with 2 entries of selection using structural vhdl

    Language:VHDL6001

  • FaisalAhmedBijoy/Digital-Logic-and-System-Design

    Digital Logic and System Design Using Logisim

    6200

  • itachi9604/4-bit-alu

    4 Bit ALU with logisim for Digital Electronics Projects

    61014

  • RomaricKc1/16-bit_computer

    16-bit machine on Logisim

    Language:Assembly6200

  • zarif98sjs/CSE-306-Computer-Architecture

    CSE-306-Computer-Architecture Offline / Assignment on ALU, Floating Point Adder and 8 bit MIPS Datapath along with pipelining

    Language:C++6303

  • EmanOthman21/PDP-11

    A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.

    Language:VHDL5203