artix-7
There are 48 repositories under artix-7 topic.
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
ultraembedded/FPGAmp
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
ultraembedded/usb2sniffer
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
vankxr/icyradio
Over-engineered SDR development board
Mario-Hero/Async-Karin
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
j3soon/Handwritten-Digit-Recognition-Painter
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
briansune/FPGA-Camera-MIPI-DVP-Verilog
FPGA Camera Parallel & MIPI Verilog
liolok/HDU_CO_Guide
HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南
chipsalliance/f4pga-xc-fasm2bels
Library to convert a FASM file into BELs importable into Vivado.
7enTropy7/Artix_7
My experiments with Nexys4 DDR Artix-7 FPGA Board
raleighlittles/Applied_Digital_Logic_Exercises_Using_FPGAs
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
Chrisdeleon91/Xilinx-Artix-7-PCIe-Project
Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.
SnrNotHere16/FPGADivisionFloatingPoint
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
whutddk/verilogRisc
基于蜂鸟E203的魔改
cajt/cmod-a7-35t_leon3
GRLIB GPL support for Digilent CMOD A7 35T board
tuhalf/SOMvhdl
A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.
34-Engineering/Virtex-HDL
This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.
hglee/AlchitryAuFpgaExample
Alchitry Au FPGA Board Example Project
Prajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
Yazmau/Verilog-Game-Tetris
A tetris-game on screen using verilog.
aryan-programmer/axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
briansune/Artix-7-Parallel-OV7670
Artix-7-Parallel-OV7670
FallingLights/Audio-Processing-Artix-7
Realtime Audio Processing on Artix-7 FPGA written in VHDL
nikhil-garg/OLED_driver_artix7
OLED driver for artix 7(Nexys 4) FPGA board.
Sped0n/ada
An Artix 7 based dual channel oscilloscope.
whutddk/YJ432-PL-PS
ARM+FPGA borad demo
ADolbyB/vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
aryan-programmer/axi_stream_array_sum_microblaze
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
briansune/Artix-7-Parallel-OV2640
Artix-7-Parallel-OV2640
briansune/Artix-7-Parallel-OV5640
Artix 7 Parallel OV5640
briansune/Artix-7-Parallel-OV7740
Artix-7-Parallel-OV7740
briansune/Artix-7-Parallel-OV9655
Artix-7-Parallel-OV9655
ilyajob05/verilog_SPI
SPI module for Nexys 4 Artix-7 FPGA Trainer Board
Ioritzaro/FPGA--Game--PingPong
Ping Pong Game in VHDL
tmahlburg/picosoc-basys3
Wrapper module for the PicoSoC to support the Digilent Basys 3