cache-coherence
There are 27 repositories under cache-coherence topic.
ic-lab-duth/NoCpad
HLS for Networks-on-Chip
vertexclique/cuneiform
Cache & In-Memory optimizations for Rust, revived from the slabs of Sumer.
mit-plv/hemiola
A Coq framework to support structural design and proof of hardware cache-coherence protocols
dsirotkin256/matching-cpp
Order matching engine
vertexclique/cuneiform-fields
Field level cache optimizations for Rust (no_std)
adamozh/cache-coherence-simulator
A cache coherence simulator for MESI, MOESI and Dragon Protocols.
muditbhargava66/CacheSimulator
A high-performance cache and memory hierarchy simulator built with modern C++17. Features configurable cache levels, advanced prefetching, MESI protocol, and detailed statistics. Ideal for computer architecture education, research, and performance analysis.
himanshu5-prog/coherent_protocols
The repository implements MOESI protocol and contains multiple cores, interconnect and memory to understance how cache coherency works and impacts performance.
adityagupta1089/Cache-Coherence-Simultaor
Simulator that simulates multiprocessor caches and involved cache coherence protocols
caesr-uwaterloo/Ditty
Repository for a predictable directory-based cache coherence for multicore safety-critical systems
ambarmodi/CacheCoherency-MOESI
Inter-cache communication protocol (MOESI) for cache coherency in a multi-processor multi-core system.
cosmin-ionita/MESI-protocol-simulator
This is a simulation of the MESI caching protocol written in C#
jkeys-ecg-nmsu/cache-simulator-with-coherency
simulation of a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.
cwang360/multicore-cache
Trace-based simulation for cache coherence in a multicore system
geokyr/advanced-topics-in-computer-architecture
Memory Hierarchy - Branch Prediction and Predictors - Cache Coherence Protocols | Advanced Topics in Computer Architecture at ECE NTUA
melver/verc3
VerC3: Verification Toolkit for C3
Nalaka1693/pthread_cache_coherence
Demonstration of how cache coherence reduce performance of a parallel program and how to overcome them.
epeec/ArgoDSM
ArgoDSM is a software distributed shared memory system which aims to provide great performance with a simplified programming model.
ishan00/multiprocessor-cache-coherence
This is our final project report for the course Computer Architecture.
KamilKrauze/StackVector
A cache-coherent stack allocated templated vector.
sebastian-wardzinski/computer-architecture
ECE552: Computer Architecture — Fall 2020.
abdullahb53/p-thread-parallel-programming
P_thread parallel programming task, cache coherency.
ehsanyousefzadehasl/MMCC
MMCC stands for Memory Model and Cache Coherence *|* In this repository, I push what I learn and code about the memory models and cache coherence protocols to be able to start to research on memory models and cache coherence protocols for GPGPUs and Heterogeneous Systems
MarceloFCandido/mesi-cache-coherence
Project about cache coherence using the MESI protocol. It is for the Computer Organization and Architecture II subject on CEFET-MG.
mtumilowicz/java17-mesi-false-sharing-processor-optimisations-workshop
Introduction to cache coherence: false sharing, MESI protocol and vectorization