cache-simulator
There are 204 repositories under cache-simulator topic.
DynamoRIO/dynamorio
Dynamic Instrumentation Tool Platform
1a1a11a/libCacheSim
a high performance library for building cache simulators
sstsimulator/sst-elements
SST Architectural Simulation Components and Libraries
tugrul512bit/LruClockCache
A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.
dasebe/webcachesim
A C++11 simulator for a variety of CDN caching policies.
spcl/haystack
Haystack is an analytical cache model that given a program computes the number of cache misses.
1a1a11a/PyMimircache
cache analysis platform developed at Emory University and CMU
seifhelal/Cache-Simulator
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
FindHao/CacheSim
A simple cache simulator
faldupriyank/grasp
Source code for the evaluated benchmarks and proposed cache management technique, GRASP, in [Faldu et al., HPCA'20].
hadibrais/archsim
A survey on architectural simulators focused on CPU caches.
uart/gltracesim
A graphics tracing and replay framework to explore system-level effects on heterogeneous CPU+GPU memory systems.
tareq-si-salem/Online-Multi-Agent-Cache-Networks
Simulator of experiments presented in "Enabling Long-term Fairness in Dynamic Resource Allocation", ACM SIGMETRICS 2023.
AleksaMCode/cache-simulator
Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.
levindoneto/Cache-Simulator
This cache simulator is used in order to simulate substitutions in cache using replacement policies (FIFO and LRU) and write back into the cache (using the write-allocate policy).
Amirhossein-Rajabpour/Cache-Simulator
Computer architecture project : Cache simulator with LRU replacement policy
dbaarda/DLFUCache
A Decaying Least Frequently Used Cache implementation.
atmughrabi/OpenGraphSim
OpenGraph is an open-source graph processing benchmarking suite written in pure C/OpenMP. Integrated with Sniper simulator.
mikhail-kukuyev/Big-Data-Processing-Algorithms
Contains implementations of cache-optimized and external memory algorithms.
Mcdonoughd/CS2011
WPI CS2011 Assembly Assignments for B-term 2017
cache-sim/cache-sim
cache simulator
cmaraziaris/MIPS-cache-config-toolkit
Set of MIPS assembly programs to help us find a secret cache configuration (cache size, block size and associativity).
muditbhargava66/CacheSimulator
A high-performance cache and memory hierarchy simulator built with modern C++17. Features configurable cache levels, advanced prefetching, MESI protocol, and detailed statistics. Ideal for computer architecture education, research, and performance analysis.
snie2012/computer-architecture-projects
Computer architecture related projects
ease-lab/grasp
Source code for the evaluated benchmarks and proposed cache management technique, GRASP, in [Faldu et al., HPCA'20].
Quamber/N-Way-Set-Associative-L1-Cache
Direct Mapped and N-Way set associative cache Simulator in C/C++ for L1 cache in Processors
abhikr360/Hierarchical-Cache-Simulator
A modular implementation of three level Cache Hierarchy
aniketp/multi-level-cache-simulator
A 3-level cache simulator for SPEC traces with various inclusion and block replacement policies
LC-John/Cache-Simulator
PKU computer organization and architecture memory hierarchy simulator LAB
radinshayanfar/ca_cache_simulator
AUT Computer Architecture Cache Simulator project
Shuiliusheng/2018
code 2018
yigitbektasgursoy/cache_simulator
A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies
Ghonimo/Design-and-Simulation-of-Split-L1-Cache-PSU-ECE585
An in-depth project focusing on the design and simulation of a split L1 cache in C++. This repository covers MESI protocol operations, comprehensive test cases, and simulation results, showcasing strategies for enhancing cache coherence and performance. This is a class project from ECE 585: Microprocessor System Design at Portland State University
Swap76/Cache_Mapping_Technique
Simulator for Direct, Associative, Set Associative Mapping Technique in Cache Allocation