chisel3
There are 115 repositories under chisel3 topic.
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
SingularityKChen/dl_accelerator
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
LoveLonelyTime/Bergamot
An exquisite superscalar RV32GC processor.
freechipsproject/diagrammer
Provides dot visualizations of chisel/firrtl circuits
microdynamics-cpu/tree-core-ide
:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
agile-hw/lectures
Lectures for the Agile Hardware Design course in Jupyter Notebooks
howardlau1999/yatcpu
Yet another toy CPU.
rhysd/riscv32-cpu-chisel
Learning how to make RISC-V 32bit CPU with Chisel
librecores/riscv-sodor
educational microarchitectures for risc-v isa
meton-robean/Vector_MulAdd_Accelerator
vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
SYSU-SCC/yatcpu-docs
Documentation for YatCPU
rameloni/tywaves-chisel
A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!
panda5mt/KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
thoughtworks/hardposit-chisel3
Chisel library for Unum Type-III Posit Arithmetic
whutddk/Rift2Core
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
jiegec/fpu-wrappers
Wrappers for open source FPU hardware implementations.
grebe/ofdm
Chisel Things for OFDM
Lampro-Mellon/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
j-marjanovic/chisel-stuff
Various examples for Chisel HDL
Starrynightzyq/soNN
A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
jiaaom/HPDLA
Systolic-array based Deep Learning Accelerator generator
ekiwi/pynq
PYNQ with Chisel and Rust
mpskex/chisel-npu
Chisel implementation of Neural Processing Unit for System on the Chip
char-fish-after-lunch/SystemOnCat
An SoC with multiple RISC-V IMA processors.
agile-hw/labs
Lab assignments for the Agile Hardware Design course
CMU-SAFARI/Pythia-HDL
Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, please read the paper that appeared in MICRO 2021 by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
horie-t/homemade-riscv-en
Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"
nhynes/chisel3-axi
Chisel3 AXI4-{Lite, Full, Stream} Definitions
j-marjanovic/chisel-bfm-tester
BFM Tester for Chisel HDL
merledu/caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
horie-t/homemade-riscv
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
merledu/magma-si
Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL
yasnakateb/CGRAs
Coarse Grained Reconfigurable Arrays with Chisel3
denishoornaert/Chisel3-Float-Type
Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)
enkerewpo/methane
A polyphonic synthesizer built on fpga and esp32
Chlorophytus/broccoli
A soft multimedia/graphics processor prototype in Chisel 3