cpu-architecture-design

There are 8 repositories under cpu-architecture-design topic.

conneroisu/mips-cpu-design
A study in MIPS microarchitecture trade-offs. This project implements three CPU designs: a single-cycle, a hardware-scheduled multicycle, and a software-scheduled pipelined core; then documents and contrasts their performance/complexity. Source is organized by variant (src_sc, src_hw, src_sw) with dedicated testbenches and write-ups.
Language:Python3 1 40
schemil053/ScheCPUEmulator
This is a simple CPU emulator with custom architecture
Language:Java2 2 01
gaidardzhiev/tortoise
custom CPU emulator and assembler
Language:C10
MEESAM749/RISC-V-PipelinedProcessor
RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE
Language:HTML10
MEESAM749/Single-Cycle-Non-Pipelined-MIPS-32-Processor
This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.
Language:C10
anpl1623/RISCV-PROCESSOR
RISCV 40 Instruction Cycle Accurate CPU Model
Language:Assembly
marianoOca/orga1_exercises
Computer Organization I exercises
Language:Python
SKCH-GE/MPU-8-bit
design of an 8-bit MPU