cpu-design

There are 42 repositories under cpu-design topic.

  • phoeniX-Digital-Design/phoeniX

    RISC-V Embedded Processor for Approximate Computing

    Language:Verilog1195480
  • CPUsimulator

    mrmcsoftware/CPUsimulator

    This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.

    Language:HTML26203
  • Linkuit-Studio

    SimonBuxx/Linkuit-Studio

    A platform for learning and experimenting with logic circuits

    Language:C++2011202

  • rauhul/ece411

    Computer Architecture UIUC SP 2018

    Language:Assembly11202

  • sarthi92/vector_processor

    Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor

    Language:Verilog10503

  • arsalanjabbari/RISCV-CPU-Design

    In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.

    Language:Verilog7101

  • martandrMC/cpu-design

    This repository contains files regarding my CPU designs

    Language:Verilog6101

  • sarthi92/cpu_cisc

    Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme

    Language:Verilog6501

  • arsalanjabbari/MIPS-CPU-Design

    This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.

    Language:Verilog5100

  • emmapaczkowski/ELEC374

    The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.

    Language:Verilog5315

  • EmreKumas/Processor_Design

    This is an implementation of a simple CPU in Logisim and Verilog.

    Language:Verilog5200

  • FISC-Project/FISC-SystemVerilog

    FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

    Language:Verilog5301

  • ArvinDelavari/Digital-Circuits-Verilog

    Sample Verilog codes for digital circuits

    Language:Verilog4101

  • ChaminduS/Building-a-RISC-V-CPU-Core

    This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

    4100

  • naderabdalghani/32-bit-risc-pipelined-processor

    Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python

    Language:VHDL4203

  • OrangeBacon/orange

    Emulator for custom computer architecture

    Language:C43122

  • MinecraftPublisher/bit

    A simple, Turing-complete and easy to recreate CPU architecture.

    Language:HTML3100

  • mrmcsoftware/MyCPUfiles

    These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.

    Language:HTML3201

  • AliAtaollahi/Computer-Architecture-Course-Projects

    Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022

    Language:Verilog2100

  • joonicks/BizzasCPU

    Bizzas CPU design

    Language:C2200

  • arashsm79/mips-hdl

    Single-cycle and multi-cycle implementation of a subset of MIPS instruction set

    Language:Verilog120

  • BrentSeidel/VHDL-CPU

    VHDL Design for a CPU

    Language:C133

  • Danial-Changez/16-Bit-MIPS-CPU

    Collaborative project using Vivado to design a CPU capable of executing R, I, and J instructions with scalable architecture.

    Language:VHDL1

  • FISC-Project/FISC-Microlang

    FISC-Microlang is a low level language below Assembly. It is used in the FISC project for creating the Microcode memory.

    Language:M41200

  • HappyFakeBoulder/FreeCPU-HARM8

    An open-source design for an 8-bit RISC CPU

    Language:Python1110

  • MarkArranz/nand2tetris

    Building a computer from first principles. Logic Gates -> CPU Architecture -> Machine Language -> VM -> High-Level Language -> Compiler -> OS -> DS & A

    Language:Hack1100

  • moreda-a/CPU-Design-RISC

    Computer Architecture Project

    Language:VHDL1200

  • phoeniX-Digital-Design/.github

    1100

  • SamEThibault/elec-374

    Verilog CPU Design Project, ELEC 374 - Digital Systems Engineering

    Language:Verilog1100

  • sarthi92/cpu_risc

    Verilog implementation of 16-bit RISC Processor with 4-stage pipeline

    Language:Verilog1201

  • ChamoDa01/Simple_CPU_Design

    A very simple microprocessor capable of executing a simple set of instructions

    Language:VHDL0110

  • DebasishPanda529/EE224_IITB-CPU

    Github repo containing all the VHDL files for the EE224 course project involving designing a rudimentary CPU.

    Language:VHDL0101

  • Karan-nevage/RISC-V-Single-Cycle-Core-Verilog-

    This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.

    Language:JavaScript0101

  • mehmetakifkoz/MARS-Web-App

    This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

    Language:JavaScript14

  • RyBlue29/Duck-Hunt

    These files make up my home made processor in Verilog. I simulated my processor on an FPGA to create an arcade style duck hunt game!

    Language:Verilog

  • TamaGo-HQ/cave_cpu

    a primitive cavecpu for primitive cavemen