digital-design
There are 261 repositories under digital-design topic.
baquer/GATE-and-CSE-Resources-for-Students
📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️
DrWaleedAYousef/Teaching
Teaching Materials for Dr. Waleed A. Yousef
iic-jku/IIC-OSIC-TOOLS
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
thedatabusdotio/fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
meiniKi/FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
medwatt/gmid
Python script for generating lookup tables for the gm/ID design methodology and much more ...
fpgaemu/fpgaemu
Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.
Ghonimo/Pre_Silicon-AHB-to_APB-Verification
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
bensampson5/libsv
An open source, parameterized SystemVerilog digital hardware IP library
adamkokeny23q2/AdobeAllInOne
AdobeAllInOne is a comprehensive suite of creative software tools developed by Adobe. It includes a range of applications for design, photography, video editing, and more, making it the ultimate solution for all your creative needs.
agicy/buptLab-digital_design
北京邮电大学 2023-2024 春季学期《数字逻辑与数字系统课程设计》——电子钟、药片装瓶系统和贪吃蛇
fcayci/vhdl-digital-design
VHDL code examples for a digital design course
muhammadaldacher/FPGA-Design-of-a-Digital-Analog-Clock-Display-using-Digilent-Basys3-Artix-7
The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.
arasgungore/VGA-based-screensaver
A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.
mnmhdanas/DA-Based-LMS-Adaptive-filter
Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .
aditeyabaral/DDCO-Lab-UE18CS207
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
alexander-titov/public
A collection of my cources, lectures, articles and presentations
arasgungore/NandGame
Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.
chaseruskin/legoHDL
An experimental package manager and development tool for Hardware Description Languages (HDL).
shahsaumya00/Floating-Point-Adder
32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog
arasgungore/256-colors-with-VGA
A VHDL-based VGA driver to display 256 different colors on a monitor.
defano/digital-design
An introduction to integrated circuit design with Verilog and the Papilio Pro development board.
mnmhdanas/Router-1-x-3-
Router 1 x 3 verilog implementation
fcayci/sv-digital-design
SystemVerilog examples for a digital design course
meiniKi/SimIO
SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.
aitesam961/16-Bit-RISC-Core-Processor
A RISC custom-ISA, 16-Bit Processor
Anand270294/AES-encryption-VSLI
EE4415 Project : AES Verilog
gabrielganzer/DLX-Microprocessor
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
hosseinfani/digital_odyssey
Materials for the Computer Science course, Digital Design (Logic Circuits)
petrsocha/hls-crypto
FPGA Cryptography for High-Level Synthesis
tatan432/AES_ENCODER
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
yuanbo-peng/Combination-Lock
This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.
mnmhdanas/UART-protocol
UART - RTL Design and Verification
HSD-ESD/VHDL-by-HGB
VHDL-by-HGB is a VS-Code extension for VHDL.
selimsandal/OneShotNPU
An NPU designed using an LLM with a single prompt
LunaQu4kez/CS207_23F_Project_GenshinKitchen
2023 Fall CS207 Digital Design Course Project with 120/100 (Full Score)