dram
There are 44 repositories under dram topic.
liquidctl/liquidctl
Cross-platform CLI and Python drivers for AIO liquid coolers and other devices
PlatformLab/RAMCloud
**No Longer Maintained** Official RAMCloud repo
umd-memsys/DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
CMU-SAFARI/ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
mjlaine/mcmcstat
MCMC toolbox for Matlab
hdl-util/sdram-controller
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
CMU-SAFARI/DRAM-Bender
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
blark/a500plus-chipram-expansion
A 1MB chip RAM expansion for the A500+
llopis/dram-tester
Sample Arduino program to test 4164 DRAM chips.
CMU-SAFARI/BEER
BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.
tukl-msd/DRAMSpec
A High-Level DRAM Timing, Power and Area Exploration Tool
dovedevic/blimp
A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.
CMU-SAFARI/CLRDRAM
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf
saiteja-talluri/Microarchitectural-attacks
Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.
CMU-SAFARI/EINSim
DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.
CMU-SAFARI/DRAM-Datasheet-Survey
A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
ppieczul/c386sx-lt-2mb-memory-module
Commodore C386SX-LT 2MB memory module schematics
wgurecky/bipymc
Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.
adarshpatil/dve
Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]
CMU-SAFARI/DRAM-Voltage-Study
Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs
CMU-SAFARI/HARP
HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/2109.12697.
comsec-group/REM
REGA Model (REM), an accurate DRAM model.
CMU-SAFARI/DIVA-DRAM
This repository provides characterization data collected over 96 DDR3 SO-DIMMs, related to the following paper: Lee et al., "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms", SIGMETRICS 2017. https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-paper.pdf
cdslaborg/paramontex
This is a repository for the ParaMonte library examples. For more information, visit:
adarshpatil/gem5gpu-hashcache
HAShCache + Intergrated CPU/GPU system simulation setup
johnzl-777/DRAMutils
A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips
pjattke/awesome-rowhammer
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
Stephen-Arsenault/DRAM-Liberator
DRAM Tester Shield for Arduino Nano
5ayam5/COL216-Minor
MIPS ISA simulator which implements non-blocking DRAM access
gaomy3832/energydram
DRAM energy calculation.
jtsimons/DRAMC
Behavioral architecture of a read/write cycle controller for a DRAM chip.
lmartorella/dram-tester
Tester for DRAM modules
Lougous/simm30
30 pins DRAM memory module
mohin7/dramkit1
Demo: https://mohin7.github.io/dramkit1/
NamhoGim/Master_thesis
Repo for my master thesis
ThexXTURBOXx/Raspberry-Pi-DRAM-PUF
Decay-based DRAM PUF for the Raspberry Pi 3B+ implemented on top of rpi-open-firmware