fpga-accelerator
There are 59 repositories under fpga-accelerator topic.
doonny/PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
google/qkeras
QKeras: a quantization deep learning library for Tensorflow Keras
jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
aliemo/transfomers-silicon-research
Research and Materials on Hardware implementation of Transformer Model
lirui-shanghaitech/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
hsharma35/dnnweaver2
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
cameronshinn/tiny-tpu
Small-scale Tensor Processing Unit built on an FPGA
Er1cZ/Deploying_CNN_on_FPGA_using_OpenCL
Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.
hossein1387/BARVINN
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
ToNi3141/Rasterix
OpenGL 1.x implementation for FPGAs
tirumalnaidu/opencl-hls-cnn-accelerator
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
RSPwFPGAs/opae-xilinx
OPAE porting to Xilinx FPGA devices.
ToNi3141/RasteriCEr
Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)
FloyedShen/mnist_hls
Lenet for MNIST handwritten digit recognition using Vivado hls tool
lirui-shanghaitech/A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
hibagus/64pointFFTProcessor
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
os-hxfan/BayesNN_FPGA
FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks.
dpretet/bster
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
leos313/DOOM_FPGA
Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
doctor3w/HLS-Cryptography-Accelerator
A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer
akzare/HardORB
TCP/IP and UDP/IP protocol stack off-loading
mmattioli/hardware-sort
Hardware-accelerated sorting algorithm
hajin-kim/FPGA_Tutorial_with_HLS
FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS
ribesstefano/Mapping-Multiple-LSTM-Models-on-FPGAs
Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.
gsneha26/Darwin-WGA
Co-processor for whole genome alignment
NikhilMukraj/spiking-neural-networks-hardware
An FPGA design for simulating biological neurons
VonTum/Dedekind
The codebase that computed the Ninth Dedekind Number
m-spr/RCEHDC
An automated HDC platform
matthiaskonrath/rc4-verilog
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
abdelazeem201/Spiking-Neural-Processor
This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.
JTP75/Advanced-Digital-Design
University of Pittsburgh ECE 1195
systemviewinc/visual-system-integrator
Visual System Integrator - Accelerate your embedded development
TurakhiaLab/DP-HLS
HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
twosixlabs/ultrazed_dev
UltraZed Development
KevinWang96/Network_Packet_Classification_on_FPGA
Network Packet classification on FPGA
SamsungLabs/Butterfly_Acc
The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"