hardware-acceleration

There are 221 repositories under hardware-acceleration topic.

  • PYNQ-2.7-MNIST

    PYNQ-Based MNIST with Tensorflow Lite

    Language:Jupyter Notebook16

  • AccANN

    🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*

    16

  • DOOM_FPGA

    Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs

    Language:C16

  • FlashySlideshows

    A GPLv3 slideshow application for OpenGL hardware accelerated slideshows , with zoom/pan effects , that will look like PS3 Slideshow

    Language:C++16

  • poetry-torch

    Installing hardware-accelerated PyTorch with Poetry on different hardware using the same `pyproject.toml`

    Language:Python14

  • YADAN-Docs

    RISC-V YADAN Core, YADAN SoC, YADAN Board's Documentation, designed for engineering education. // 鸭蛋的文档。

    14

  • akashi

    A next-generation video editor

    Language:C++14

  • wildcat

    C++ 2D Game Engine

    Language:C++14

  • RTHS

    Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm

    Language:Verilog13

  • HLS_for_CNN

    This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.

    Language:C13

  • CompressedLUT

    A tool to generate optimized hardware files for univariate functions.

    Language:C++12

  • MultiScalarMultiplication

    Chisel module for performing Multi-Scalar Multiplication

    Language:Scala12

  • FFT-R22SDF

    R22SDF FFT VLSI/FPGA investigate and implementation

    Language:Verilog12

  • npuemulator

    A neural network fast inference library implementing Coral Edge TPU emulator using AVX2.

    Language:C++12

  • ros2_examples

    Example packages for ROS2

    Language:C++11

  • adaptive_component

    A composable container for Adaptive ROS 2 Node computations. Select between FPGA, CPU or GPU at run-time.

    Language:C++11

  • Matmul

    Matrix Multiplication in Hardware

    Language:C11

  • Chisel3-Float-Type

    Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)

    Language:Scala11

  • GPU-Audio

    browser based audio processing using the GPU

    Language:JavaScript11
  • Innervator

    Innervator

    Innervator: Hardware Acceleration for Neural Networks

    Language:VHDL10

  • MNIST-FPGA-Accelarator

    MNIST accelerator using pynq-z2 and the binary qunatization

    Language:C++10

  • acceleration_firmware_kv260

    KV260 firmware. Package for enabling hardware acceleration capabilities in ROS 2 with KV260.

    Language:CMake10

  • BAVCL

    Hardware-accelerated Vector Compute Library for .NET Containing Quality of life improvements and functionality intended for data science, graphical processing and GPGPU.

    Language:C#10

  • nonideality-aware-mnn-training

    Code used in the paper “Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks”

    Language:Python10

  • ssdfa

    Github page for SSDFA

    Language:Python10

  • processing-element

    A configurable processing element for deep neural network accelerators

    Language:Scala10

  • processing-engine

    A Scala w/ Chisel based implementation of a processing engine generator for neural network accelerators.

    Language:Jupyter Notebook10

  • acceleration_firmware_kr260

    KR260 Ubuntu 22.04 firmware. Package for enabling hardware acceleration capabilities in ROS 2 Humble with KR260 and Ubuntu 22.04.

    Language:CMake9

  • bitar

    Simplify accessing hardware compression/decompression accelerators

    Language:C++9

  • KRS

    Kria Robotics Stack (KRS) documentation. KRS is a ROS 2 superset for industry built around the Kria SOM portfolio. Simplifies the use of hardware acceleration in robotics.

    Language:CSS9

  • verify-beacon

    💡 Compute and verify the SHA-256 random beacons used in the Zcash MPC ceremonies.

    Language:Rust9

  • MasterThesis

    VHDL implementation of a customizable CNN

    Language:VHDL9

  • Advanced-Digital-Design

    University of Pittsburgh ECE 1195

    Language:VHDL8

  • HLS-Zybo

    A collection of HLS IP designs for Zybo-Z2

    Language:VHDL8

  • HSA-on-FPGA

    integration of FPGAs in HSA compatible systems

    Language:Tcl8

  • CRC32

    32-bit CRC Hardware Accelerator and Custom Instructions implemented (in Verilog) in Altera's FPGA board.

    Language:C8