instruction-decoding
There are 10 repositories under instruction-decoding topic.
LekKit/RVVM
The RISC-V Virtual Machine
DispatchCode/x64-Instruction-Decoder
An x86/x64 instruction disassembler written in C
OPSphystech420/CGuardProbe
Memory Engine and Scanner for iOS/MacOS using Mach API
Danijel-Korent/RISC-V-emulator
RISC-V emulator/simulator in Python
BeRo1985/pasriscv
PasRISCV is a RV64GC RISC-V emulator, which is implemented in Object Pascal
uros-bojanic/8-bit-computer
[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.
BeRo1985/pasriscvemu
The PasVulkan-based emulator frontend for the PasRISCV RV64GC RISC-V emulator
keneoneth/InstrHexBinDecConvertDecoder-Release
a web based front end only helper tool that provides Instruction Decoder and Converter in hexadecimal binary decimal form encoding of different ISA
leonlafa/sap1-logisim
A simulation of a Simple-As-Possible (SAP) computer, implemented in Logisim Evolution.
christalphilip/mips-disassembler
A Java-based MIPS disassembler that converts binary machine code into readable MIPS assembly instructions, supporting key R- and I-format instructions with branch target address resolution.