logic-synthesis
There are 59 repositories under logic-synthesis topic.
SJTU-ECTL/HEDALS
Highly efficient delay-driven approximate logic synthesis
marcocosta97/SOP-ApproximateLogicSynthesis
Approximate Logic Synthesis and Bi-Decomposition of Sum Of Products forms
NTU-ALComLab/ext-folding
A circuit folding interface in ABC system
NYU-MLDA/ABC-RL
This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
Po-Chun-Chien/LUT-Net
An implementation of LUT-Net learning procedure
AlishKanani/ACA-CSU_Approximate-Adders
MATLAB and HDL models of ACA-CSU approximate adders
atul-khobragade/Digital-Logic-Synthesis
To generate an electrical circuit from the given input and output boolean values.
boschmitt/losys
Logic synthesis and verification framework
hriener/aig
C++ header-only And-Inverter graph (AIG) library
NYU-MLDA/ALMOST
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning
Po-Chun-Chien/FringeDT
An implementation of binary decision tree with fringe-features extraction.
born-2learn/DRiLLS
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization
changmg/espresso
Mirror of espresso, a two-level logic synthesis tool
ginomcfino/CELLO-3.0
CELLO - Cell Genetic Circuit Design Automation. Python code built from the ground up, which branched off into the repositories Cello-V3-Core and UCFormatter.
NikolaosGian/VLSI-ASIC-IC
An application using Cadence IC Package
NTU-ALComLab/IWLS2021
Code repository for the IWLS 2021 Programming Contest
NYU-MLDA/RTL_dataset
Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys
snowkylin/npn
A boolean matcher that computes the NPN canonical representative for a given boolean function.
BUPTslb/LIMGEN
This project will be the beginning of my research life!
raescartin/Recompiler
An approach to algorithm optimization through circuit minimization techniques.
reity/article-permutation-circuit-synthesis
This article describes how embedded languages and recursion can be used to create a tool that synthesizes a relatively efficient logical circuit for any chosen permutation of the set of all bit vectors of some fixed length.
wei-shen-wang/LSV-PA
Wei-Shen's Fork 2023 Fall Logic Synthesis and Verification: Programming Assignments
wei-shen-wang/LSV_Final
2023 Logic Synthesis and Verification Final Project