mips-architecture
There are 265 repositories under mips-architecture topic.
Specy/asm-editor
A modern webapp to write, run and learn M68K, MIPS, RISC-V, X86 assembly
neelkshah/MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
aeris170/MARS-Theme-Engine
It's all coming back into focus!
RomeoMe5/DDLM
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
ffcabbar/MIPS-Assembly-Language-Examples
:heavy_check_mark: Examples to learn Mips
ljlin/MIPS48PipelineCPU
5 stage pipelined MIPS-32 processor
SilenceX12138/MIPS-Microsystems
A computer system containing CPU, OS and Compiler under MIPS architecture.
maze1377/pipeline-mips-verilog
A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
Ingenic-community/linux
Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.
edoardottt/asm-snippets
Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree :floppy_disk:
tjsparks5/Pipelined-MIPS-Processor
Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.
JoMedeiros/MIPSnake
A snake game developed in assembly for MIPS processor
i-evi/sse2msa
A C/C++ header file that converts Intel SSE intrinsics to MIPS/MIPS64 MSA intrinsics.
jiajudu/mips
32-bit MIPS CPU
acai422/Bubble-Sort
Bubble Sort in MIPS
aliiimaher/MIPS-Verilog
MIPS architecture implemented in Verilog.
amirHosseinEz/MIPS-architecture
MIPS architecture implemented in Verilog.
respinha/mips-systemc
Assignment from the Advanced Computer Architecture class.
Elzawawy/mips-processor-simulator
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
MIPT-ILab/mips-traces
MIPS programs with MARS system calls
Passant-Abdelgalil/MIPS-Processor-Harvard-Architecture
A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.
saliherdemk/Mips-Datapath-Simulator
This is a website for demonstration of how most of the basic instructions work in MIPS architecture
zarif98sjs/CSE-306-Computer-Architecture
CSE-306-Computer-Architecture Offline / Assignment on ALU, Floating Point Adder and 8 bit MIPS Datapath along with pipelining
Devorein/aisem
A web app to convert MIPS assembly code to machine code
ElectroBoy404NotFound/pico-uMIPS
Dmitry Grinberg's uMIPS emulator on the Raspberry Pi Pico
EmanOthman21/MIPS-Pipelined-Processor
This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.
holden-davis-uca/MARS-UCA
Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.
mongrelgem/cMIPS
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
cissagatto/MIPS32BitsCheatsheet
Cheatsheet completinha do MIPS 32 bits - MIPS Technologies
SentinelSw/MipsStaticStackAnalyzer
An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler
viniciusfinger/assembly-mips
Lasalle University - Computer Architecture 2020/1 - Assembly + MIPS architecture
akankshac-073/MIPS-5-stage-pipelined-control-and-datapath
Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.
Choaib-ELMADI/32-bit-processor-with-vhdl
Forked from ZIKOAR's 32-bit-processor-with-vhdl repository.
CodeDroid999/MIPS-Assembler-in-C
An Assembler to read and parse MIPS Assembly code and then generate an output file
pauldeng/qt5-openwrt-package
Qt 5 package for OpenWRT