netlist-simulation-

There are 2 repositories under netlist-simulation- topic.

  • arhamhashmi01/openlane-verification

    This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

    Language:Verilog1100

  • muhammadtalhasami/openlane

    This is my openlane repository in which we perform synthesis of our design/module.

    Language:Tcl1100