nexys4ddr
There are 39 repositories under nexys4ddr topic.
shinde-shantanu/FPGA_TDC
Time to Digital Converter on an FPGA
santifs/ultrasonic-sensor
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
zhongyuchen/mips-32bit
Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board
g0kul/Game-of-Balance-on-Nexys4DDR
Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board.
luminoso/cr-countones
Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs
yidiwang21/Nexys-4-Projects
Mini projects based on Xilinx Nexys 4 DDR
7enTropy7/Artix_7
My experiments with Nexys4 DDR Artix-7 FPGA Board
nickschiffer/parallel_unsigned_integer_multiplier
Xilinx Vivado Project
edw4rdyao/sdcard_digital_recognition
FPGA based SD card reads and displays pictures and performs digital recognition experiments.
Louis-GUENEGO/NEXYS4ddr_microphone
An audio project with the NEXYS 4 ddr
SnrNotHere16/FPGADivisionFloatingPoint
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
nickschiffer/fsm_calculator
A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board
SnrNotHere16/Asynchronous-FIFO
An FPGA implementation of Cummings' Asynchronous FIFO
sromerop/ArtificialNeuron
It is my Final Degree Project of Grado de Tecnologías y Servicios de Telecomunicación in Universidad Politécnica de Madrid
davismariotti/HelicopterGame
A helicopter game written for the Nexys 4 DDR Board in VHDL
iBug/Nexys4-DDR-stopwatch
A stopwatch on Digilent Nexys4 DDR written in Verilog
santifs/simon-game-vhdl
VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.
shinesunnysom/Biofeedback-Game-System
CECS 490A/490B Course; Senior Project Design
shreegw/FPGA-Thermostat-Controller
A Thermostat controller designed using the temperature sensor on the Nexys-4 module
brown9804/NexysDDR4-RISC-V_picorv32
Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU
cesar-avalos3/ROM_Controller
Nexys 4 DDR - Rom Controller
Elon-Wang/Breakout
Using the FPGA board Nexys Artix-7 to design a breakout game with vhdl language.
cmfcmf/vhdl-demo
A simple text editor written in VHDL for the Nexys 4 DDR Evaluation board.
jideoyelayo1/PongGameVerilog
A Pong Game made in Verilog
lild4d4/usm_microcontroller_v1
Undergraduate level RISC-V microcontroller
nickschiffer/cla_adder_7seg
4bit_CLA_Adder_7seg in Xilinx Vivado Verilog
SnrNotHere16/BreakoutZyboVGAScore
Usese the zybo and nexys 4 ddr to play a game of breakout.
Yellowflash-070/Digitalclock12Hr
A 12 Hour Digital Clock Implemented on Nexys4 DDR FPGA board using Verilog HDL.
GraceSevillano/RTIC-project-Antoine-s-army
This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed
TahirZia-1/Digital-Clock-Verilog
This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.
austinbhale/MIPS-Stacker
Stacker Arcade Game in MIPS Assembly Language
ishifr/fpga_prototyping_codes
FPGA prototyping by Verilog examples kitobini o'qish davomida yozilgan kodlar to'plami. Nexys4DDR(Artix-7) dev board'dan foydalanilgan. A collection of code written while reading the book FPGA prototyping by Verilog examples. Nexys4DDR(Artix-7) dev board is used
Juanx65/Aguilera_Mardones_T4_3_1_IPD432
Tarea 4 Parte 3.1 IPD432 - Procesador de vectores para Nexys4 DDR
LuisMLopez-dev/Double-Dabble-Algorithm
This is a VHDL code for converting a binary number to a BCD (binary-coded decimal) number using the Double Dabble Algorithm.
syedahmedullah14/AI-on-air
A cutting-edge AI SaaS platform that enables users to create, discover, and enjoy podcasts with advanced features like text-to-audio conversion with multi-voice AI, podcast thumbnail image generation, and seamless playback. The platform is built using Next.js, TypeScript, Convex, OpenAI, Stripe, Clerk, ShadCN, and Tailwind CSS.
TahirZia-1/UART
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.