opensta

There are 5 repositories under opensta topic.

  • vsdip/vsdflow

    VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

    Language:Coq13001

  • kanndil/PathView

    An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

    Language:HTML2231

  • Pa1mantri/VSD_Hardware_Design

    Pre and Post Synthesis Simulation of a Design VSDMemSOC

    Language:Verilog2201

  • Pa1mantri/VSDMemSOC

    VSDMemSOC Implementation flow:: RTL2GDSII

    Language:Verilog1100

  • Pa1mantri/NASSCOM_SoC_Design

    Complete RTL to GDSII flow of a picorv32a core

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