parameterised-verilog

There are 1 repositories under parameterised-verilog topic.

  • Sooryakiran/dotV

    A library to generate parameterized Verilog code from C++. Allows you to assemble Verilog modules in C++, use C++ syntax to dynamically generate complex connections, parameterize code, and ultimately get the Verilog code automatically generated.

    Language:C++3201