pulpino

There are 8 repositories under pulpino topic.

  • klessydra/T13x

    An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

    Language:VHDL455011

  • klessydra/T02x

    A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores

    Language:VHDL23204

  • klessydra/T03x

    A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores

    Language:VHDL13212

  • kactus2/pulpinoexperiment

    IP-XACT packaging of Pulpino by pulp-platform.org: https://github.com/pulp-platform/pulpino

    Language:Verilog10733

  • rafafigueredoviana/RISCV_MCU_CYCLONEV

    A basic implementation of the RISCV core into a DE10nano FPGA board.

    Language:SystemVerilog7005

  • cad-polito-it/pulpino_ri5cy_stls

    Stuck-At Software Test Libraries for the pulpino-ri5cy SoC

    Language:Assembly4400

  • coastalwhite/pulpino-top-level-cw305

    The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core

    Language:Verilog4102
  • neumann_fpga

    SubhamRath/neumann_fpga

    FPGA emulation for project neumann.

    101