quartus2

tocache/Altera-Cyclone-II-FPGA

Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II

NeilNie/LC-3

Verilog Implementation of the LC-3 Processor. DA CS 603

topofkeks/arilla

Arilla - a RISC-V based microcomputer system, with a PS2 mouse controller and 12-bit RGB SVGA graphics card, running Arilla Paint.

DavidRosero/FPGAWorldCodes

Ejemplos de codigo con implementación en hardware para la tarjeta Cyclone IV lenguaje VHDL

furkankayar/DEUARC

DEUARC RISC computer design in Quartus II 13.0

joonicks/BizzasCPU

Bizzas CPU design

LoicKonan/Logic-Design

Logic Design.

pa-tiq/DE0_FIR_Filter

FIR filter for Altera DE0 EP3C16F484C6N Created on top of SURF VHDL FIR Filter

Chrisdeleon91/Altera-DE1-VGA-Interface

Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.

Everloom-129/ECE385-Digital-Systems-Lab

The goal of ECE 385 course is to teach students to design, build, and test/debug a digital system, which can be a 16-bit microprocessor, a dedicated logic core, or a system-on-a-chip (SoC) platform

jrg94/EECS301

CWRU's Logic Lab

andrerocco/sistemas-digitais-multiplicadores

Diferentes multiplicadores implementados em hardware.

Erfangholiz/My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

jimfangx/DE2-70-Bringup

Assorted Verilog that brings up different elements (VGA, Ethernet, Switches, LED, LCD, etc.) of the terasIC DE2-70 Development Board.

KonstantinosVasilopoulos/aueb_processor

A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.

LukaSimovic/Catch-the-square-FPGA

The player needs to click on the square with a computer mouse before it disappears. The score is shown on the seven-segment FPGA board display.

mdivjak/Icy_Tower

Icy Tower FPGA Cyclone III Game

MohammadMahdi-Abdolhosseini/Computer-Architecture-Lab

Computer Architecture Lab - Assignments - Fall 2023

zenek65/Quartus-HEX-16bit

convert avr 8bit intel HEX to Altera 16 bit HEX format

abdelrahman-alaa-10/FIFO_Memory

A digital design implementation of a FIFO memory circuit using VHDL simulated in Quartus.

AtlasFPGA/PINOUT_ATLAS_CYC1000

Subida del fichero TCL asociado al pineado de la placa CYC1000, Con sus múltiples variantes recogidas en un fichero de texto.

Charlie-Ramirez-Animation-Studios-de-MX/VHDL-Basicos

Programas Basicos en Lenguaje VHDL de Diseño Logico y Diseño de Circuitos Digitales para Uso y simulacion con QuartusII y los FPGA Cyclone III de Altera (Compilados y compatibles con la FPGA EP3C16F484C6N) Para Practica en la Licenciatura de Ingenieria Electrica Electronica e Ingenieria en Computación Bajo Licencia MIT

daerong/VHDL_Study

Quartus II, MX6Q를 사용한 HDL 학습

errray/fpga-spaceship

This space ship game project, where the spaceship is positioned at the center and objects coming from different directions can be hit using FPGA buttons, has been implemented with Verilog coding in quartus environment for Altera System-on-Chip (SoC) FPGA and VGA for display.

jesusjimsa/Desarrollo-de-Hardware-Digital-UGR

Prácticas de la asignatura de Desarrollo de Hardware Digital en la UGR

LelePG/implementacoes_VHDL

Implementações feitas em VHDL nas disciplinas de Circuitos Digitais I, Circuitos Digitais II e Sistemas Digitais Avançados

marcelovalois/projetoULA

Projeto de uma ULA feito em Quartus II para a disciplina de Sistemas Digitais (2019.1)

markods/FpgaTetris

MoeeinAali/CE323-CA

Solutions to Dr. Arshadi's CE323: Computer Architecture Course (Sharif University of Technology - Spring 2024)

NeilNie/LearnVerilog_Lab1

Learning Verilog, Quartus & FPGA. DA CS 603

rusito-23/arki

Quartus II Pipelined Processor