rv32im
There are 22 repositories under rv32im topic.
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
sysprog21/shecc
A self-hosting and educational C optimizing compiler
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
kuopinghsu/srv32
Simple 3-stage pipeline RISC-V processor
ultraembedded/riscv-linux-boot
Trivial RISC-V Linux binary bootloader
rob-ng15/Silice-Playground
Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
ultraembedded/riscv_sbc
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
ultraembedded/minispartan6-audio
miniSpartan6+ (Spartan6) FPGA based MP3 Player
swetland/os-workshop
Some materials and sample source for RV32 OS projects.
cepdnaclk/e16-co502-RV32IM-pipeline-implementation-group1
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.
jesseopdenbrouw/riscv-rv32
A synthesizable RISC-V RV32IM microcontroller written in VHDL
solomspd/RISC-V-CPU
RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards
ultraembedded/riscv-linux
RISC-V Linux Port (supporting RV32IM - CPUs without atomic extensions)
ArvinDelavari/RV32-APX
32 Bits RISC-V Processor with Approximate Functions
tvlad1234/rv32adventure
Becoming acquainted with the RISC-V ISA by writing an emulator
saleh1204/rv32im
RV32IM System-on-Chip (SoC)
ArthurFerreira2/herve
herve, the rv simulator is a simple risc-v RV32IMA ISA simulator.
hari-haran05/Hi-Five_CPU
This is an RV32_IM riscv cpu core. Its a non-pipelined core with MULW instruction alone from M extension.
jesseopdenbrouw/thuas-riscv
The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbs microcontroller
Juminiy/sysy
sysy lang by c executable in risc-v platform.
splinedrive/TangNano-9K-example
TangNano-9K-example project with kianRiscV cpu
Sup3Legacy/proto-core
Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.